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| v1.0 Automotive ProASIC3 Flash Family FPGAs Features and Benefits High-Temperature AEC-Q100-Qualified Devices * Grade 2 105C TA (115C TJ) * Grade 1 125C TA (135C TJ) * PPAP Documentation (R) Low Power * 1.5 V Core Voltage * Support for 1.5-V-Only Systems * Low-Impedance Flash Switches High-Performance Routing Hierarchy * Segmented, Hierarchical Routing and Clock Structure * High-Performance, Low-Skew Global Network * Architecture Supports Ultra-High Utilization Firm-Error Immune * Only Automotive FPGAs to Offer Firm-Error Immunity * Can Be Used without Configuration Upset Risk Advanced I/O * * * * * * * * * * * 700 Mbps DDR, LVDS-Capable I/Os 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages--up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and A3P1000) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold-Sparing I/Os Programmable Output Slew Rate and Drive Strength Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-Compatible Packages across the Automotive ProASIC(R)3 Family High Capacity * 60 k to 1 M System Gates * Up to 144 kbits of SRAM * Up to 300 User I/Os Reprogrammable Flash Technology * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Automotive Process * Live-at-Power-Up (LAPU) Level 0 Support * Single-Chip Solution * Retains Programmed Design when Powered Off On-Chip User Nonvolatile Memory * 1 kbit of FlashROM with Synchronous Interface High Performance * 350 MHz System Performance * 3.3 V, 66 MHz 64-Bit PCI Clock Conditioning Circuit (CCC) and PLL * Six CCC Blocks, One with an Integrated PLL * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range (1.5 MHz up to 350 MHz) In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents (anti-tampering) SRAMs * Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations available) Automotive ProASIC3 Product Family ProASIC3 Devices System Gates VersaTiles (D-flip-flops) RAM kbits (1,024 bits) 4,608-Bit Blocks FlashROM Bits Secure (AES) ISP Integrated PLL in CCCs VersaNet Globals* I/O Banks Maximum User I/Os Package Pins VQFP FBGA A3P060 60 k 1,536 18 4 1k Yes 1 18 2 96 VQ100 FG144 A3P125 125 k 3,072 36 8 1k Yes 1 18 2 133 VQ100 FG144 A3P250 250 k 6,144 36 8 1k Yes 1 18 4 157 VQ100 FG144, FG256 A3P1000 1M 24,576 144 32 1k Yes 1 18 4 300 FG144, FG256, FG484 Note: *Six chip-wide (main) globals and three additional global networks in each quadrant are available. January 2008 (c) 2008 Actel Corporation I I/Os Per Package ProASIC3 Devices A3P060 A3P125 A3P250 I/O Type Differential I/O Pairs Differential I/O Pairs - 25 44 74 Single-Ended I/O 2 - 97 177 300 Single-Ended I/O 2 A3P1000 Single-Ended I/O Package VQ100 FG144 FG256 FG484 Notes: 71 96 - - 71 97 - - Single-Ended I/O 68 97 157 - 13 24 38 - 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 Flash Family FPGAs handbook to ensure complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of available single-ended I/Os by two. 3. FG256 and FG484 are footprint-compatible packages. Automotive ProASIC3 Ordering Information A3P1000 _ 1 FG G 144 T Application (Temperature Range) T = Grade 2 and Grade 1 AECQ100 Grade 2 = 105C TA and 115C TJ Grade 1 = 125C TA and 135C TJ Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS-Compliant (Green) Packaging Package Type VQ = Very Thin Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number Automotive ProASIC3 Devices A3P060 = 60,000 System Gates A3P125 = 125,000 System Gates A3P250 = 250,000 System Gates A3P1000 = 1,000,000 System Gates Note: Minimum order quantities apply. Contact your local Actel sales office for details. II v1.0 Automotive ProASIC3 Flash Family FPGAs Temperature Grade Offerings Package VQ100 FG144 FG256 FG484 Notes: 1. C = Commercial temperature range: 0C to 70C 2. I = Industrial temperature range: -40C to 85C 3. T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100 Grade 2 = 105C TA and 115C TJ Grade 1 = 125C TA and 135C TJ 4. Specifications for Commercial and Industrial grade devices can be found in the ProASIC3 Flash Family FPGAs handbook. A3P060 C, I, T C, I, T - - A3P125 C, I, T C, I, T - - A3P250 C, I, T C, I, T C, I, T - A3P1000 - C, I, T C, I, T C, I, T Speed Grade and Temperature Grade Matrix Temperature Grade T (Grade 1 and Grade 2), Commercial, Industrial Notes: 1. T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100 Grade 2 = 105C TA and 115C TJ Grade 1 = 125C TA and 135C TJ 2. Specifications for Commercial and Industrial grade devices can be found in the ProASIC3 Flash Family FPGAs handbook. Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. Std. -1 v1.0 III 1 - Automotive ProASIC3 Device Family Overview General Description Automotive ProASIC3 nonvolatile flash technology gives automotive system designers the advantage of a secure, low-power, single-chip solution that is live at power-up (LAPU). Automotive ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. Automotive ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). Automotive ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of SRAM and up to 300 user I/Os. Automotive ProASIC3 devices are the only firm-error-immune automotive grade FPGAs. Firm-error immunity makes them ideally suited for demanding applications in powertrain, safety, and telematics-based subsystems, where firm-error failure is not an option. Firm errors in SRAM-based FPGAs can result in high defect levels in field-deployed systems. These unavoidable defects must be considered separately from standard defects and failure mechanisms when looking at overall system quality and reliability. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based Automotive ProASIC3 devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Flash-based FPGAs are LAPU Class 0 devices, offering the lowest available power in a single-chip device and providing firm-error immunity. The Automotive ProASIC3 family device architecture mitigates the need for ASIC migration at high user volumes. This makes the Automotive ProASIC3 family a costeffective ASIC replacement solution, especially for automotive applications. Security The nonvolatile, flash-based Automotive ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. Automotive ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. Automotive ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in Automotive ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES128 (FIPS192) bit block cipher encryption standard. The AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. Automotive ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. Automotive ProASIC3 devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed Automotive ProASIC3 device cannot be read back, although secure design verification is possible. Additionally, security features of Automotive ProASIC3 devices provide anti-tampering protection. Security, built into the FPGA fabric, is an inherent component of the Automotive ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout v1.0 1-1 Automotive ProASIC3 Device Family Overview techniques have been used to make invasive attacks extremely difficult. The Automotive ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure. An Automotive ProASIC3 device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based Automotive ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based Automotive ProASIC3 devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based Automotive ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and external clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the Automotive ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based Automotive ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of Automotive ProASIC3 flash-based FPGAs. Once it is programmed, the flash cell configuration element of Automotive ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Low Power Flash-based Automotive ProASIC3 devices exhibit very low power characteristics, similar to those of an ASIC, making them an ideal choice for power-sensitive applications. Automotive ProASIC3 devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. Automotive ProASIC3 devices also have low dynamic power consumption to further maximize power savings. 1 -2 v1.0 Automotive ProASIC3 Flash FPGAs Advanced Flash Technology The Automotive ProASIC3 family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary Automotive ProASIC3 architecture provides granularity comparable to standardcell ASICs. The Automotive ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4): * * * * * FPGA VersaTiles Dedicated FlashROM Dedicated SRAM memory Extensive CCCs and PLLs Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the Automotive ProASIC3 core tile as either a threeinput lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generationarchitecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of Automotive ProASIC3 devices via an IEEE 1532 JTAG interface. v1.0 1-3 Automotive ProASIC3 Device Family Overview Bank 0 CCC RAM Block 4,608-Bit SRAM or FIFO Block Bank 1 Bank 0 Bank 0 I/Os VersaTile Bank 1 ISP AES Decryption User Nonvolatile FlashROM Bank 1 Charge Pumps Figure 1-1 * Automotive ProASIC3 Device Architecture Overview with Two I/O Banks (A3P060 and A3P125) Bank 0 CCC RAM Block 4,608-Bit SRAM or FIFO Block Bank 3 Bank 1 Bank 1 I/Os VersaTile Bank 3 ISP AES Decryption User Nonvolatile FlashROM Bank 2 Charge Pumps RAM Block 4,608-Bit SRAM or FIFO Block (A3P600 and A3P1000) Figure 1-2 * Automotive ProASIC3 Device Architecture Overview with Four I/O Banks (A3P600 and A3P1000) 1 -4 v1.0 Automotive ProASIC3 Flash FPGAs VersaTiles The Automotive ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The Automotive ProASIC3 VersaTile supports the following: * * * * All 3-input logic functions--LUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y LUT-3 Y Figure 1-3 * VersaTile Configurations User Nonvolatile FlashROM Actel Automotive ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * * * * * * * * Unique protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, infotainment systems) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management The FlashROM is written using the standard Automotive ProASIC3 IEEE 1532 JTAG programming interface. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel Automotive ProASIC3 development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. v1.0 1-5 Automotive ProASIC3 Device Family Overview SRAM Automotive ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. PLL and CCC Automotive ProASIC3 devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each member of the Automotive ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: * * * * * * * * * * * * Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz Clock delay adjustment via programmable and fixed delays from -7.56 ns to +11.12 ns 2 programmable delay types for clock skew minimization Clock frequency synthesis (for PLL only) Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). Output duty cycle = 50% 1.5% or better (for PLL only) Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) Maximum acquisition time is 300 s (for PLL only) Low power consumption of 5 mW Exceptional tolerance to input period jitter-- allowable input jitter is up to 1.5 ns (for PLL only) Four precise phases; maximum misalignment between adjacent phases of 40 ps x 350 MHz / fOUT_CCC (for PLL only) Additional CCC specifications: Global Clocking Automotive ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The Automotive ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). Automotive ProASIC3 FPGAs support many different I/O standards--single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported. 1 -6 v1.0 Automotive ProASIC3 Flash FPGAs Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * * Single-Data-Rate applications Double-Data-Rate applications--DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications Automotive ProASIC3 banks for the A3P250 and A3P1000 devices support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Part Number and Revision Date Part Number 51700099-001-0 Revised January 2008 v1.0 1-7 Automotive ProASIC3 Device Family Overview Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 1 -8 v1.0 Automotive ProASIC3 DC and Switching Characteristics 2 - Automotive ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximums are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 22 on page 2-2 is not implied. Table 2-1 * Symbol VCC VJTAG VPUMP VCCPLL VCCI VMV VI Absolute Maximum Ratings Parameter DC core supply voltage JTAG DC voltage Programming voltage Analog power supply (PLL) DC I/O output buffer supply voltage DC I/O input buffer supply voltage I/O input voltage Limits -0.3 to 1.65 -0.3 to 3.75 -0.3 to 3.75 -0.3 to 1.65 -0.3 to 3.75 -0.3 to 3.75 -0.3 V to 3.6 V (when I/O hot insertion mode is enabled) -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 TJ 2 Units V V V V V V V Storage temperature Junction temperature -65 to +150 +150 C C Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-3 on page 2-3. 2. For flash programming and retention maximum limits, refer to Figure 2-1 on page 2-2. For recommended operating limits, refer to Table 2-2 on page 2-2. v1.0 2-1 Automotive ProASIC3 DC and Switching Characteristics Table 2-2 * Symbol TJ VCC VJTAG VPUMP VCCPLL Recommended Operating Conditions Parameter Junction temperature 1.5 V DC core supply voltage JTAG DC voltage Programming voltage Programming Mode Operation Analog power supply (PLL) 3 Automotive Grade 1 Automotive Grade 2 Units -40 to +135 1.425 to 1.575 1.4 to 3.6 3.0 to 3.6 0 to 3.6 1.4 to 1.6 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 -40 to +115 1.425 to 1.575 1.4 to 3.6 3.0 to 3.6 0 to 3.6 1.4 to 1.6 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 C V V V V V V V V V V V VCCI and VMV 1.5 V DC supply voltage 1.8 V DC supply voltage 2.5 V DC supply voltage 3.3 V DC supply voltage LVDS/B-LVDS/M-LVDS differential I/O LVPECL differential I/O Notes: 1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-14 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank. 2. All parameters representing voltages are measured with respect to GND unless otherwise specified. 3. VPUMP can be left floating during operation (not programming mode). Tj (C) 70 85 100 105 110 115 120 125 130 135 140 145 150 HTR Lifetime (yrs) 102.7 43.8 20.0 15.6 12.3 9.7 7.7 6.2 5.0 4.0 3.3 2.7 2.2 110 100 90 80 70 60 50 40 30 20 10 0 70 85 100 105 110 115 120 125 130 135 140 145 150 Temperature (C) Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage. Figure 2-1 * High-Temperature Data Retention (HTR) 2 -2 Years v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-3 * Overshoot and Undershoot Limits (as measured on quiet I/Os) Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle 10% 5% 3V 3.3 V 3.6 V Notes: 1. The duration is allowed at one out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 2. This table refers only to overshoot/undershoot limits for simultaneously switching I/Os and does not provide PCI overshoot/undershoot limits. 10% 5% 10% 5% 10% 5% Maximum Overshoot/ Maximum Overshoot/ Undershoot (115C) Undershoot (135C) 0.81 V 0.90 V 0.80 V 0.90 V 0.79 V 0.88 V N/A N/A 0.72 V 0.82 V 0.72 V 0.81 V 0.69 V 0.79 V N/A N/A VCCI and VMV 2.7 V or less I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every ProASIC(R)3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2 on page 2-4. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-4). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: * * During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation v1.0 2-3 Automotive ProASIC3 DC and Switching Characteristics VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI Figure 2-2 * I/O State as a Function of VCCI and VCC Voltage Levels Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 2-1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-4 on page 2-5. P = Power dissipation 2 -4 v1.0 Automotive ProASIC3 DC and Switching Characteristics Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 110C. EQ 2-2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. 110C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = -------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.951 W 20.5C/W ja (C/W) EQ 2-2 Table 2-4 * Package Thermal Resistivities ja Package Type Very Thin Quad Flat Pack (VQFP) Fine Pitch Ball Grid Array (FBGA) Device All devices See note* See note* See note* A3P1000 A3P1000 A3P1000 Pin Count 100 144 256 484 144 256 484 jc 10.0 3.8 3.8 3.2 6.3 6.6 8.0 Still Air 35.3 26.9 26.6 20.5 31.6 28.1 23.3 200 ft./min. 29.4 22.9 22.8 17.0 26.2 24.4 19.0 500 ft./min. 27.1 21.5 21.5 15.9 24.2 22.7 16.7 Units C/W C/W C/W C/W C/W C/W C/W * This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information will be available in future revisions of the datasheet. Temperature and Voltage Derating Factors Table 2-5 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 115C, VCC = 1.425 V) -40C 0.83 0.79 0.76 0C 0.88 0.83 0.80 25C 0.90 0.85 0.82 70C 0.95 0.90 0.87 85C 0.97 0.92 0.88 115C 1.00 0.95 0.91 125C 1.01 0.96 0.93 135C 1.02 0.97 0.94 Array Voltage VCC (V) 1.425 1.5 1.575 v1.0 2-5 Automotive ProASIC3 DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-6 * Quiescent Supply Current Characteristics A3P060 Typical (25C) Maximum (Automotive Grade 1) - 135C Maximum (Automotive Grade 2) - 115C 2 mA 53 mA 26 mA A3P125 2 mA 53 mA 26 mA A3P250 3 mA 106 mA 53 mA A3P1000 8 mA 265 mA 131 mA Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-7 and Table 2-10 on page 2-8. Power per I/O Pin Table 2-7 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings1 Applicable to Advanced I/O Banks VMV (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 2.5 3.3 2.26 5.72 1.20 1.87 3.3 2.5 1.8 1.5 3.3 3.3 - - - - - - 16.69 5.12 2.13 1.45 18.11 18.11 Static Power PDC2 (mW)1 Dynamic Power PAC9 (W/MHz)2 2 -6 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-8 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings1 Applicable to Standard Plus I/O Banks VMV (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. Table 2-9 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 Applicable to Advanced I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VMV. 3. PAC10 is the total dynamic power measured on VCCI and VMV. - - 2.5 3.3 7.74 19.54 88.92 166.52 35 35 35 35 10 10 3.3 2.5 1.8 1.5 3.3 3.3 - - - - - - 468.67 267.48 149.46 103.12 201.02 201.02 VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 2.5 1.8 1.5 3.3 3.3 - - - - - - 16.72 5.14 2.13 1.48 18.13 18.13 Static Power PDC2 (mW)1 Dynamic Power PAC9 (W/MHz)2 v1.0 2-7 Automotive ProASIC3 DC and Switching Characteristics Table 2-10 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 Applicable to Standard Plus I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VMV. 3. PAC10 is the total dynamic power measured on VCCI and VMV. 35 35 35 35 10 10 3.3 2.5 1.8 1.5 3.3 3.3 - - - - - - 452.67 258.32 133.59 92.84 184.92 184.92 VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (W/MHz)3 2 -8 v1.0 Automotive ProASIC3 DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-11 * Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices Device Specific Dynamic Power (W/MHz) Parameter PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13 PAC14 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standard-dependent) Contribution of an I/O output pin (standard-dependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Static PLL contribution Dynamic contribution for PLL A3P1000 A3P250 A3P125 A3P060 14.50 2.48 11.00 1.58 0.81 0.12 0.07 0.29 0.29 0.70 See Table 2-7 on page 2-6. See Table 2-7 and Table 2-10 on page 2-8. 25.00 30.00 2.55 mW 2.60 11.00 0.81 9.30 0.81 * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Actel Libero(R) Integrated Design Environment (IDE). Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * * * * * * * * The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-12 on page 2-11. Enable rates of output buffers--guidelines are provided for typical applications in Table 213 on page 2-12. Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-13 on page 2-12. The calculation should be repeated for each clock domain defined in the design. v1.0 2-9 Automotive ProASIC3 DC and Switching Characteristics Methodology Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption--PSTAT PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK NSPINE is the number of global spines used in the user design--guidelines are provided in Table 2-12 on page 2-11. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. Combinatorial Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. FCLK is the global clock signal frequency. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-11. Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number VersaTiles used as sequential modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-12 on page 2-11. 2 -1 0 v1.0 Automotive ProASIC3 DC and Switching Characteristics I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-12. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-13 on page 2-12. FCLK is the global clock signal frequency. RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. 3 FWRITE-CLOCK is the memory write clock frequency. is the RAM enable rate for write operations--guidelines are provided in Table 2-13 on page 2-12. PPLL = PAC13 + PAC14 * FCLKOUT PLL Contribution--PPLL FCLKIN is the input clock frequency. FCLKOUT is the output clock frequency.1 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * * The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: - - - - - - Bit 0 (LSB) = 100% Bit 1 Bit 2 ... Bit 7 (MSB) = 0.78125% Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 = 50% = 25% Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-12 * Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10% 1 2 1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution. v1.0 2 - 11 Automotive ProASIC3 DC and Switching Characteristics Table 2-13 * Enable Rate Guidelines Recommended for Power Calculation Component Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5% 1 2 3 User I/O Characteristics Timing Model I/O Module (non-registered) Combinational Cell Y tPD = 0.67 ns Combinational Cell Y tPD = 0.58 ns tDP = 1.66 ns Combinational Cell Y tPD = 1.04 ns I/O Module (registered) tPY = 1.29 ns LVPECL (applicable to Advanced I/O banks only) D Q tPD = 0.60 ns Combinational Cell Y tICLKQ = 0.29 ns tISUD = 0.31 ns Input LVTTL Clock Register Cell tPY = 0.94 ns (Advanced I/O banks) I/O Module (non-registered) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) tCLKQ = 0.66 ns tSUD = 0.51 ns tPY = 1.47 ns Input LVTTL Clock tPY = 0.94 ns (Advanced I/O banks) D Q Combinational Cell Y tPD = 0.56 ns tCLKQ = 0.66 ns tSUD = 0.51 ns Input LVTTL Clock tPY = 0.94 ns (Advanced I/O banks) Register Cell D Q D tPD = 0.56 ns I/O Module (non-registered) LVTTL Output Drive Strength = 12 mA High Slew Rate tDP = 3.25 ns (Advanced I/O banks) I/O Module (non-registered) LVTTL Output drive Strength = 8 mA High Slew Rate tDP = 4.52 ns (Advanced I/O banks) I/O Module (non-registered) LVCMOS 1.5 V Output Drive Strength = 4 mA High Slew Rate tDP = 4.89 ns (Advanced I/O banks) I/O Module (registered) Q LVTTL 3.3 V Output Drive Strength = 12 mA tDP = 3.25 ns High Slew Rate (Advanced I/O banks) LVPECL (applicable to Advanced I/O banks only) Combinational Cell Y tOCLKQ = 0.70 ns tOSUD = 0.37 ns Figure 2-3 * Timing Model Operating Conditions: -1 Speed, Automotive Grade 2 Temp. Range (TJ = 115C), Worst Case VCC = 1.425 V 2 -1 2 v1.0 Automotive ProASIC3 DC and Switching Characteristics tPY tDIN PAD D Y Q DIN To Array CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) I/O Interface VIH Vtrip Vtrip VCC 50% Y GND tPY (R) tPY (F) VCC 50% DIN GND tDOUT (R) Figure 2-4 * Input Buffer Timing Model and Delays (example) PAD VIL 50% 50% tDOUT (F) v1.0 2 - 13 Automotive ProASIC3 DC and Switching Characteristics tDOUT DQ D From Array I/O Interface CLK tDP PAD Std Load tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) tDOUT VCC 50% VCC (F) 0V DOUT tDOUT (R) 50% D DOUT 50% 50% VOH 0V Vtrip PAD tDP (R) Figure 2-5 * Output Buffer Model and Delays (example) Vtrip VOL tDP (F) 2 -1 4 v1.0 Automotive ProASIC3 DC and Switching Characteristics tEOUT D E Q tZL, tZH, tHZ, tLZ, tZLS, tZHS CLK EOUT D D Q DOUT CLK PAD I/O Interface tEOUT = MAX(tEOUT(r), tEOUT(f)) VCC D VCC E 50% tEOUT (R) 50% EOUT tZL PAD Vtrip VOL 50% tEOUT (F) VCC 50% tHZ 90% VCCI 50% tZH VCCI Vtrip 10% VCCI 50% tLZ VCC D VCC E 50% tEOUT (R) VCC EOUT PAD Vtrip VOL 50% tZLS 50% VOH 50% tZHS Vtrip 50% tEOUT (F) Figure 2-6 * Tristate Output Buffer Timing Model and Delays (example) v1.0 2 - 15 Automotive ProASIC3 DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels - Default I/O Software Settings Table 2-14 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Advanced I/O Banks I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X VIL Drive Slew Strength Rate Min, V Max, V 12 mA 12 mA 12 mA 12 mA High High High High -0.3 -0.3 -0.3 -0.3 0.8 0.7 0.30 * VCCI VIH Min, V 2 1.7 0.7 * VCCI Max, V 3.6 3.6 3.6 3.6 VOL Max, V 0.4 0.7 0.45 VOH Min, V 2.4 1.7 VCCI - 0.45 IOL 12 12 12 12 IOH 12 12 12 12 mA mA 0.35 * VCCI 0.65 * VCCI 0.25 * VCCI 0.75 * VCCI Per PCI specifications Per PCI-X specifications Note: Currents are measured at 125C junction temperature. Table 2-15 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X VIL Drive Slew Max, V Strength Rate Min, V 12 mA 12 mA 8 mA 4 mA High High High High -0.3 -0.3 -0.3 -0.3 0.8 0.7 0.35 * VCCI 0.30 * VCCI VIH Min, V 2 1.7 0.65 * VCCI 0.7 * VCCI Max, V 3.6 3.6 3.6 3.6 VOL Max, V 0.4 0.7 0.45 0.25 * VCCI VOH Min, V 2.4 1.7 VCCI - 0.45 0.75 * VCCI IOL IOH mA mA 12 12 8 4 12 12 8 4 Per PCI specifications Per PCI-X specifications Note: Currents are measured at 125C junction temperature. Table 2-16 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Standard I/O Banks I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS VIL Drive Slew Max, V Strength Rate Min, V 8 mA 8 mA 4 mA 2 mA High High High High -0.3 -0.3 -0.3 -0.3 0.8 0.7 0.30 * VCCI VIH Min, V 2 1.7 0.7 * VCCI Max, V 3.6 3.6 3.6 3.6 VOL Max, V 0.4 0.7 0.45 VOH Min, V 2.4 1.7 VCCI - 0.45 IOL 8 8 4 2 IOH 8 8 4 2 mA mA 0.35 * VCCI 0.65 * VCCI 0.25 * VCCI 0.75 * VCCI Note: Currents are measured at 125C junction temperature. 2 -1 6 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-17 * Summary of Maximum and Minimum DC Input Levels Applicable to Automotive Grade 1 and Grade 2 Automotive Grade 11 IIL DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes: 1. Automotive range Grade 1 (-40C < TJ < 135C) 2. Automotive range Grade 2 (-40C < TJ < 115C) A 10 10 10 10 10 10 IIH A 10 10 10 10 10 10 Automotive Grade 2 2 IIL A 15 15 15 15 15 15 IIH A 15 15 15 15 15 15 Summary of I/O Timing Characteristics - Default I/O Software Settings Table 2-18 * Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI Measuring Trip Point (Vtrip) 1.4 V 1.2 V 0.90 V 0.75 V 0.285 * VCCI (RR) 0.615 * VCCI (FF) 3.3 V PCI-X 0.285 * VCCI (RR) 0.615 * VCCI (FF) Table 2-19 * I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tHZ tZH tLZ tZL tZHS tZLS Parameter Definition Data-to-Pad delay through the Output Buffer Pad-to-Data delay through the Input Buffer Data-to-Output Buffer delay through the I/O interface Enable-to-Output Buffer Tristate Control delay through the I/O interface Input Buffer-to-Data delay through the I/O interface Enable-to-Pad delay through the Output Buffer--HIGH to Z Enable-to-Pad delay through the Output Buffer--Z to HIGH Enable-to-Pad delay through the Output Buffer--LOW to Z Enable-to-Pad delay through the Output Buffer--Z to LOW Enable-to-Pad delay through the Output Buffer with delayed enable--Z to HIGH Enable-to-Pad delay through the Output Buffer with delayed enable--Z to LOW v1.0 2 - 17 Automotive ProASIC3 DC and Switching Characteristics Table 2-20 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Automotive-Case Conditions: TJ = 115C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Advanced I/O Banks External Resistor () Capacitive Load (pF) Drive Strength (mA) tE OU T (ns) Slew Rate tDOUT (ns) tDIN (ns) tZLS (ns) tDP (ns) tZH (ns) tPY (ns) tZL (ns) tLZ (ns) tHZ (ns) tZHS (ns) - - I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X LVDS LVPECL Notes: 12 mA 12 mA 12 mA 12 mA Per PCI spec High 35 pF High 35 pF High 35 pF High 35 pF - - - - 2 0.53 3.25 0.04 0.94 0.38 3.31 1.51 2.96 1.88 5.37 2.71 ns 0.53 3.28 0.04 1.19 0.38 3.34 3.16 1.77 1.80 5.39 5.22 ns 0.53 3.25 0.04 1.12 0.38 1.89 1.63 3.41 3.75 3.06 2.82 ns 0.53 3.75 0.04 1.32 0.38 2.18 1.91 3.63 3.87 3.35 3.11 ns 0.53 2.12 0.04 0.78 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns High 10 pF 25 Per PCI-X High 10 pF 25 2 0.53 2.47 0.04 0.77 0.38 1.23 0.91 2.57 2.96 2.41 2.11 ns spec 24 mA 24 mA High High - - - - 0.53 1.68 0.04 1.47 0.53 1.66 0.04 1.29 - - - - - - - - - - - - ns ns 1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-47 for connectivity. This resistor is not required during normal operation. 2 -1 8 v1.0 Units Automotive ProASIC3 DC and Switching Characteristics Table 2-21 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Automotive-Case Conditions: TJ = 115C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Standard Plus I/O Banks Capacitive Load (pF) Drive Strength (mA) External Resistor Slew Rate tEO UT tDOUT I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes: 12 mA 12 mA 8 mA 4 mA Per PCI spec High 35 pF High 35 pF High 35 pF High 35 pF - - - - 2 0.55 3.01 0.04 0.95 0.39 1.74 1.43 2.65 3.06 1.74 1.43 ns 0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns 0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns 0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns High 10 pF 25 Per PCI-X High 10 pF 25 2 0.55 2.19 0.04 0.79 0.39 1.27 0.94 2.65 3.06 1.27 0.94 ns spec 1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-47 for connectivity. This resistor is not required during normal operation. v1.0 2 - 19 Units tZHS tDIN tDP tHZ tZH tPY tLZ tZL tZLS Automotive ProASIC3 DC and Switching Characteristics Table 2-22 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Automotive-Case Conditions: TJ = 135C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Advanced I/O Banks External Resistor () Capacitive Load (pF) Drive Strength (mA) tE OU T (ns) Slew Rate tDOUT (ns) tDIN (ns) tZLS (ns) tDP (ns) tZH (ns) tPY (ns) tZL (ns) tLZ (ns) tHZ (ns) tZHS (ns) - - I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X LVDS LVPECL Notes: 12 mA 12 mA 12 mA 12 mA Per PCI spec High 35 pF High 35 pF High 35 pF High 35 pF - - - - 2 0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns 0.55 3.39 0.04 1.23 0.39 3.45 3.27 1.83 1.86 5.58 5.39 ns 0.55 3.36 0.04 1.16 0.39 1.95 1.68 3.52 3.88 3.16 2.92 ns 0.55 3.88 0.04 1.37 0.39 2.25 1.98 3.75 4.00 3.46 3.21 ns 0.55 2.19 0.04 0.81 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns High 10 pF 25 Per PCI-X High 10 pF 25 2 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns spec 24 mA 24 mA High High - - - - 0.55 1.74 0.04 1.52 0.55 1.71 0.04 1.34 - - - - - - - - - - - - ns ns 1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-47 for connectivity. This resistor is not required during normal operation. 2 -2 0 v1.0 Units Automotive ProASIC3 DC and Switching Characteristics Table 2-23 * Summary of I/O Timing Characteristics--Software Default Settings -1 Speed Grade, Automotive-Case Conditions: TJ = 115C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Standard Plus I/O Banks Capacitive Load (pF) Drive Strength (mA) External Resistor tEO UT (ns) Slew Rate tDOUT (ns) tPY (ns) tZHS (ns) tDIN (ns) tDP (ns) tZL (ns) tZLS (ns) tZH (ns) tHZ (ns) tLZ (ns) I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes: 12 mA 12 mA 8 mA 4 mA Per PCI spec High 35 pF High 35 pF High 35 pF High 35 pF - - - - 2 0.55 3.36 0.04 0.97 0.39 3.42 1.56 3.05 1.94 5.55 2.80 ns 0.55 3.05 0.04 1.23 0.39 3.11 2.99 1.56 1.69 5.23 5.11 ns 0.55 3.73 0.04 1.16 0.39 3.65 3.86 1.62 1.68 5.78 5.99 ns 0.55 4.60 0.04 1.35 0.39 4.61 5.05 2.07 1.85 6.74 7.18 ns 0.55 2.55 0.04 0.82 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns High 10 pF 25 Per PCI-X High 10 pF 25 2 0.55 2.55 0.04 0.79 0.39 1.27 0.94 2.65 3.06 2.49 2.18 ns spec 1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-47 for connectivity. This resistor is not required during normal operation. v1.0 2 - 21 Units Automotive ProASIC3 DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-24 * Input Capacitance Symbol CIN CINCLK Definition Input capacitance Input capacitance on the clock pin Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF Table 2-25 * I/O Output Buffer Maximum Resistances1 Applicable to Advanced I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 2.5 V LVCMOS 2 mA 6 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI , drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c Per PCI/PCI-X specification RPULL-DOWN ()2 100 100 50 50 25 17 11 100 50 25 20 11 200 100 50 50 20 20 200 100 67 33 33 25 RPULL-UP ()3 300 300 150 150 75 50 33 200 100 50 40 22 225 112 56 56 22 22 224 112 75 37 37 75 2 -2 2 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-26 * I/O Output Buffer Maximum Resistances1 Applicable to Standard Plus I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 2.5 V LVCMOS 2 mA 6 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c Table 2-27 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () VCCI 3.3 V 2.5 V 1.8 V 1.5 V Notes: 1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) Min. 10 k 11 k 18 k 19 k Max. 45 k 55 k 70 k 90 k R(WEAK PULL-DOWN)2 () Min. 10 k 12 k 17 k 19 k Max. 45 k 74 k 110 k 140 k Per PCI/PCI-X specification RPULL-DOWN ()2 100 100 50 50 25 25 100 50 25 200 100 50 50 200 100 0 RPULL-UP ()3 300 300 150 150 75 75 200 100 50 225 112 56 56 224 112 0 v1.0 2 - 23 Automotive ProASIC3 DC and Switching Characteristics Table 2-28 * I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 2.5 V LVCMOS 2 mA 6 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 3.3 V PCI/PCI-X * TJ = 100C Per PCI/PCI-X specification IOSL (mA)* 27 27 54 54 109 127 181 27 27 54 54 109 127 181 18 37 74 87 124 11 22 44 51 74 74 16 33 39 55 55 109 IOSH (mA)* 25 25 51 51 103 132 268 25 25 51 51 103 132 268 16 32 65 83 169 9 17 35 45 91 91 13 25 32 66 66 103 2 -2 4 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-29 * I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 2.5 V LVCMOS 2 mA 6 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 3.3 V PCI/PCI-X * TJ = 100C The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-30 * Duration of Short Circuit Event before Failure Temperature -40C 0C 25C 70C 85C 100C 110C 125C 135 Time before Failure > 20 years > 20 years > 20 years 5 years 2 years 6 months 3 months 25 days 12 days Per PCI/PCI-X specification IOSL (mA)* 27 27 54 54 109 109 18 37 74 11 22 44 44 16 33 109 IOSH (mA)* 25 25 51 51 103 103 16 32 65 9 17 35 35 13 25 103 v1.0 2 - 25 Automotive ProASIC3 DC and Switching Characteristics Table 2-31 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS LVDS/B-LVDS/M-LVDS/LVPECL Input Rise/Fall Time (min.) No requirement No requirement Input Rise/Fall Time (max.) 10 ns * 10 ns * Reliability 20 years (110C) 10 years (100C) * The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure there is no excessive noise coupling into input signals. Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor-Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-32 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.8 0.8 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2 4 6 8 2 4 6 8 27 27 54 54 109 127 181 25 25 51 51 103 132 268 10 10 10 10 10 10 10 10 10 10 10 10 10 10 12 12 16 16 24 24 2 -2 6 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-33 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.8 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 2 4 6 8 2 4 6 8 27 27 54 54 109 109 25 25 51 51 103 103 10 10 10 10 10 10 10 10 10 10 10 10 12 12 16 16 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-7 * AC Loading Table 2-34 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 35 * Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points. v1.0 2 - 27 Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-35 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA Speed Grade STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 24 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-36 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA Speed Grade STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 24 mA STD -1 tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 11.47 9.75 8.13 6.92 8.13 6.92 6.24 5.31 5.82 4.95 5.42 4.61 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.14 0.97 1.14 0.97 1.14 0.97 1.14 0.97 1.14 0.97 1.14 0.97 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 11.68 9.94 8.28 7.05 8.28 7.05 6.36 5.41 5.93 5.04 5.52 4.70 tZH 9.95 8.46 7.03 5.98 7.03 5.98 5.45 4.63 5.10 4.34 5.08 4.32 tLZ 1.46 1.46 1.65 1.65 1.65 1.65 1.77 1.77 1.80 1.80 1.83 1.83 tHZ 1.33 1.33 1.65 1.65 1.65 1.65 1.85 1.85 1.90 1.90 2.10 2.11 tZLS 14.18 12.06 10.79 9.17 10.79 9.17 8.86 7.53 8.43 7.17 8.02 6.82 tZHS 12.449 10.59 9.526 8.103 9.526 8.103 7.946 6.76 7.604 6.468 7.581 6.449 Units ns ns ns ns ns ns ns ns ns ns ns ns tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 8.56 7.28 5.49 4.67 5.49 4.67 3.95 3.36 3.73 3.17 3.44 2.92 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.14 0.97 1.14 0.97 1.14 0.97 1.14 0.97 1.14 0.97 1.14 0.97 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 8.72 7.42 5.59 4.75 5.59 4.75 4.02 3.42 1.84 1.84 1.70 1.70 tZH 7.37 6.27 4.55 3.87 4.55 3.87 1.56 1.56 1.42 1.42 1.17 1.17 tLZ 1.46 1.46 1.65 1.65 1.65 1.65 3.59 3.05 3.65 3.10 3.72 3.16 tHZ 1.42 1.42 1.74 1.74 1.74 1.74 1.94 1.94 4.11 3.50 4.54 3.86 tZLS 11.22 9.54 8.09 6.88 8.09 6.88 6.52 5.55 3.05 3.05 2.91 2.91 tZHS 9.866 8.393 7.05 5.997 7.05 5.997 2.795 2.797 2.651 2.653 2.405 2.407 Units ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -2 8 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-37 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA Speed Grade STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-38 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA Speed Grade STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 10.82 9.21 7.49 6.37 7.49 6.37 5.64 4.80 5.64 4.80 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.12 0.95 1.12 0.95 1.12 0.95 1.12 0.95 1.12 0.95 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 11.02 9.38 7.63 6.49 7.63 6.49 5.75 4.89 5.75 4.89 tZH 9.42 8.01 6.58 5.60 6.58 5.60 5.04 4.29 5.04 4.29 tLZ 1.26 1.26 1.43 1.43 1.43 1.43 1.54 1.54 1.54 1.54 tHZ 1.20 1.20 1.48 1.49 1.48 1.49 1.67 1.67 1.67 1.67 tZLS 11.02 9.38 7.63 6.49 7.63 6.49 5.75 4.89 5.75 4.89 tZHS 9.419 8.012 6.58 5.598 6.58 5.598 5.042 4.289 5.042 4.289 Units ns ns ns ns ns ns ns ns ns ns tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 8.06 6.85 5.03 4.28 5.03 4.28 3.53 3.01 3.53 3.01 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.12 .095 1.12 0.95 1.12 0.95 1.12 0.95 1.12 0.95 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 8.20 6.98 5.13 4.36 5.13 4.36 1.74 1.74 1.74 1.74 tZH 7.03 5.98 4.27 3.63 4.27 3.63 1.43 1.43 1.43 1.43 tLZ 1.26 1.26 1.42 1.42 1.42 1.42 3.12 2.65 3.12 2.65 tHZ 1.27 1.27 1.56 1.56 1.56 1.56 3.60 3.06 3.60 3.06 tZLS 8.20 6.98 5.13 4.36 5.13 4.36 1.74 1.74 1.74 1.74 tZHS 7.027 5.978 4.267 3.63 4.267 3.63 1.427 1.428 1.427 1.428 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 29 Automotive ProASIC3 DC and Switching Characteristics Table 2-39 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA Speed Grade STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 24 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-40 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA Speed Grade STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 24 mA STD -1 tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 11.09 9.44 7.87 6.69 7.87 6.69 6.04 5.14 5.63 4.79 5.25 4.46 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.10 0.94 1.10 0.94 1.10 0.94 1.10 0.94 1.10 0.94 1.10 0.94 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 11.30 9.61 8.02 6.82 8.02 6.82 6.15 5.23 5.74 4.88 5.34 4.55 tZH 9.63 8.19 6.80 5.78 6.80 5.78 5.27 4.48 4.94 4.20 4.92 4.18 tLZ 1.41 1.41 1.59 1.59 1.59 1.59 1.71 1.71 1.74 1.74 1.77 1.77 tHZ 1.29 1.29 1.59 1.60 1.59 1.60 1.79 1.79 1.84 1.84 2.04 2.04 tZLS 13.72 11.67 10.43 8.88 10.43 8.88 8.57 7.29 8.16 6.94 7.76 6.60 tZHS 12.04 10.25 9.22 7.84 9.22 7.84 7.69 6.54 7.36 6.26 7.34 6.24 Units ns ns ns ns ns ns ns ns ns ns ns ns tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 8.28 7.05 5.31 4.52 5.31 4.52 3.82 3.25 3.60 3.07 3.33 2.83 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.10 0.94 1.10 0.94 1.10 0.94 1.10 0.94 1.10 0.94 1.10 0.94 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 8.44 7.18 5.41 4.60 5.41 4.60 3.89 3.31 1.78 1.78 1.64 1.64 tZH 7.13 6.06 4.40 3.74 4.40 3.74 1.51 1.51 1.37 1.37 1.13 1.13 tLZ 1.42 1.42 1.60 1.60 1.60 1.60 3.47 2.96 3.53 3.00 3.60 3.06 tHZ 1.37 1.37 1.68 1.68 1.68 1.68 1.88 1.88 3.98 3.38 4.39 3.74 tZLS 10.85 9.23 7.83 6.66 7.83 6.66 6.31 5.37 2.95 2.95 2.81 2.82 tZHS 9.55 8.12 6.82 5.80 6.82 5.80 2.70 2.71 2.57 2.57 2.33 2.33 Units ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -3 0 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-41 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA Speed Grade STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-42 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA Speed Grade STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 tDOUT 0.63 0.55 0.63 0.55 0.63 0.55 0.63 0.55 0.63 0.55 tDP 10.47 9.21 7.25 6.37 7.25 6.37 5.46 4.80 5.46 4.80 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.08 0.95 1.08 0.95 1.08 0.95 1.08 0.95 1.08 0.95 tEOUT 0.45 0.39 0.45 0.39 0.45 0.39 0.45 0.39 0.45 0.39 tZL 10.66 9.38 7.38 6.49 7.38 6.49 5.56 4.89 5.56 4.89 tZH 9.11 8.01 6.37 5.60 6.37 5.60 4.88 4.29 4.88 4.29 tLZ 1.22 1.26 1.38 1.43 1.38 1.43 1.49 1.54 1.49 1.54 tHZ 1.16 1.20 1.44 1.49 1.44 1.49 1.61 1.67 1.61 1.67 tZLS 10.66 9.38 7.38 6.49 7.38 6.49 5.56 4.89 5.56 4.89 tZHS 9.11 8.01 6.37 5.60 6.37 5.60 4.88 4.29 4.88 4.29 Units ns ns ns ns ns ns ns ns ns ns tDOUT 0.63 0.55 0.63 0.55 0.63 0.55 0.63 0.55 0.63 0.55 tDP 7.79 6.85 4.87 4.28 4.87 4.28 3.42 3.01 3.42 3.01 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.08 0.95 1.08 0.95 1.08 0.95 1.08 0.95 1.08 0.95 tEOUT 0.45 0.39 0.45 0.39 0.45 0.39 0.45 0.39 0.45 0.39 tZL 7.94 6.98 4.96 4.36 4.96 4.36 1.69 1.74 1.69 1.74 tZH 6.80 5.98 4.13 3.63 4.13 3.63 1.38 1.43 1.38 1.43 tLZ 1.22 1.26 1.38 1.42 1.38 1.42 3.02 2.65 3.02 2.65 tHZ 1.23 1.27 1.51 1.56 1.51 1.56 3.48 3.06 3.48 3.06 tZLS 7.94 6.98 4.96 4.36 4.96 4.36 1.69 1.74 1.69 1.74 tZHS 6.80 5.98 4.13 3.63 4.13 3.63 1.38 1.43 1.38 1.43 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 31 Automotive ProASIC3 DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 V-tolerant input buffer and push-pull output buffer. Table 2-43 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 6 mA 12 mA 16 mA 24 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. Table 2-44 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 6 mA 12 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 -0.3 -0.3 -0.3 -0.3 -0.3 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 3.6 3.6 3.6 3.6 3.6 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 2 6 12 16 24 2 6 12 16 24 18 37 74 87 124 Max., mA1 A2 A2 16 32 65 83 169 10 10 10 10 10 10 10 10 10 10 Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 -0.3 -0.3 -0.3 0.7 0.7 0.7 1.7 1.7 1.7 3.6 3.6 3.6 0.7 0.7 0.7 1.7 1.7 1.7 2 6 12 2 6 12 18 37 74 Max., mA1 A2 A2 16 32 65 10 10 10 10 10 10 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-8 * AC Loading Table 2-45 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 2.5 Measuring Point* (V) 1.2 CLOAD (pF) 35 * Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points. 2 -3 2 v1.0 Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-46 * 2.5 V LVCMOS High Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 6 mA STD -1 12 mA STD -1 16 mA STD -1 24 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-47 * 2.5 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 6 mA STD -1 12 mA STD -1 16 mA STD -1 24 mA STD -1 tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 12.12 10.31 8.24 7.01 6.91 5.88 6.44 5.48 6.16 5.24 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 12.54 10.67 9.07 7.71 7.04 5.99 6.56 5.58 6.15 5.23 tZH 12.74 10.84 8.74 7.43 6.62 5.63 6.18 5.26 6.16 5.24 tLZ 1.48 1.48 1.68 1.69 1.82 1.83 1.86 1.86 1.90 1.90 tHZ 1.19 1.20 1.57 1.57 1.80 1.80 1.86 1.86 2.10 2.10 tZLS 15.04 12.80 11.57 9.84 9.54 8.11 9.06 7.71 8.65 7.36 tZHS 15.243 12.966 11.237 9.559 9.117 7.756 8.678 7.382 8.657 7.364 Units ns ns ns ns ns ns ns ns ns ns tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 9.69 8.24 5.78 4.91 3.98 3.39 3.75 3.19 3.45 2.94 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 8.76 7.45 5.63 4.79 4.05 3.45 1.85 1.85 1.70 1.71 tZH 9.69 8.24 5.78 4.91 3.84 3.27 1.69 1.69 1.35 1.35 tLZ 1.48 1.48 1.68 1.69 1.82 1.83 3.76 3.20 3.84 3.27 tHZ 1.25 1.25 1.62 1.63 1.86 1.86 3.97 3.38 4.47 3.80 tZLS 11.26 9.58 8.13 6.92 6.55 5.58 3.06 3.06 2.92 2.92 tZHS 12.187 10.367 8.277 7.04 6.338 5.392 2.926 2.929 2.585 2.586 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 33 Automotive ProASIC3 DC and Switching Characteristics Table 2-48 * 2.5 V LVCMOS High Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 6 mA STD -1 12 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-49 * 2.5 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 6 mA STD -1 12 mA STD -1 tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 tDP 12.12 10.31 8.24 7.01 6.30 5.35 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.45 1.23 1.45 1.23 1.45 1.23 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 tZL 11.89 10.12 8.39 7.14 6.41 5.45 tZH 12.12 10.31 8.23 7.00 6.16 5.24 tLZ 1.25 1.25 1.43 1.43 1.56 1.56 tHZ 1.08 1.08 1.42 1.42 1.63 1.63 tZLS 14.39 12.24 10.89 9.26 8.91 7.58 tZHS 14.622 12.438 10.73 9.128 8.656 7.364 Units ns ns ns ns ns ns tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 tDP 9.26 7.87 5.43 4.62 3.59 3.05 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.45 1.23 1.45 1.23 1.45 1.23 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 tZL 8.28 7.05 5.19 4.42 3.65 3.11 tZH 9.26 7.87 5.43 4.62 3.51 2.99 tLZ 1.24 1.24 1.43 1.43 1.56 1.56 tHZ 1.12 1.13 1.47 1.47 1.69 1.69 tZLS 10.78 9.17 7.69 6.55 6.15 5.23 tZHS 11.756 10 7.926 6.743 6.012 5.114 Units ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -3 4 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-50 * 2.5 V LVCMOS High Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 6 mA STD -1 12 mA STD -1 16 mA STD -1 24 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-51 * 2.5 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 6 mA STD -1 12 mA STD -1 16 mA STD -1 24 mA STD -1 tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 11.73 9.98 7.97 6.78 6.68 5.69 6.24 5.30 5.96 5.07 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 12.14 10.32 8.77 7.46 6.81 5.79 6.35 5.40 5.95 5.06 tZH 12.33 10.49 8.45 7.19 6.40 5.45 5.98 5.08 5.96 5.07 tLZ 1.43 1.43 1.63 1.63 1.77 1.77 1.80 1.80 1.84 1.84 tHZ 1.16 1.16 1.51 1.52 1.74 1.74 1.80 1.80 2.03 2.03 tZLS 14.55 12.38 11.19 9.52 9.23 7.85 8.77 7.46 8.37 7.12 tZHS 14.75 12.55 10.87 9.25 8.82 7.50 8.40 7.14 8.38 7.12 Units ns ns ns ns ns ns ns ns ns ns tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 9.37 7.97 5.59 4.75 3.85 3.28 3.63 3.08 3.34 2.84 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 8.47 7.21 5.45 4.63 3.92 3.34 1.79 1.79 1.65 1.65 tZH 9.37 7.97 5.59 4.75 3.71 3.16 1.64 1.64 1.31 1.31 tLZ 1.43 1.43 1.63 1.63 1.77 1.77 3.64 3.09 3.72 3.16 tHZ 1.21 1.21 1.57 1.57 1.80 1.80 3.84 3.27 4.32 3.68 tZLS 10.89 9.27 7.87 6.69 6.34 5.39 2.96 2.96 2.82 2.82 tZHS 11.79 10.03 8.01 6.81 6.13 5.22 2.83 2.83 2.50 2.50 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 35 Automotive ProASIC3 DC and Switching Characteristics Table 2-52 * 2.5 V LVCMOS High Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 6 mA STD -1 12 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-53 * 2.5 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 6 mA STD -1 12 mA STD -1 tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 tDP 11.73 9.98 7.97 6.78 6.09 5.18 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.40 1.19 1.40 1.19 1.40 1.19 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 tZL 11.51 9.79 8.12 6.91 6.20 5.28 tZH 11.73 9.98 7.96 6.77 5.96 5.07 tLZ 1.21 1.21 1.38 1.39 1.51 1.51 tHZ 1.04 1.04 1.37 1.37 1.58 1.58 tZLS 13.93 11.85 10.54 8.96 8.62 7.33 tZHS 14.15 12.03 10.38 8.83 8.38 7.12 Units ns ns ns ns ns ns tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 tDP 8.95 7.62 5.25 4.47 3.47 2.95 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.40 1.19 1.40 1.19 1.40 1.19 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 tZL 8.01 6.82 5.03 4.27 3.53 3.01 tZH 8.95 7.62 5.25 4.47 3.40 2.89 tLZ 1.20 1.20 1.38 1.38 1.51 1.51 tHZ 1.09 1.09 1.42 1.42 1.63 1.63 tZLS 10.43 8.87 7.44 6.33 5.95 5.06 tZHS 11.37 9.68 7.67 6.52 5.82 4.95 Units ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -3 6 v1.0 Automotive ProASIC3 DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-54 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. Table 2-55 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. -0.3 -0.3 -0.3 -0.3 VIL Max., V VIH Min., V VOL Max., V Max., V 3.6 3.6 3.6 3.6 0.45 0.45 0.45 0.45 VOH Min., V VCCI - 0.45 VCCI - 0.45 VCCI - 0.45 VCCI - 0.45 IOL IOH IOSL IOSH IIL IIH -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VIL Max., V VIH Min., V VOL Max., V Max., V 3.6 3.6 3.6 3.6 3.6 3.6 0.45 0.45 0.45 0.45 0.45 0.45 VOH Min., V VCCI - 0.45 VCCI - 0.45 VCCI - 0.45 VCCI - 0.45 VCCI - 0.45 VCCI - 0.45 IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 4 6 8 2 4 6 8 11 22 44 51 74 74 9 17 35 45 91 91 10 10 10 10 10 10 10 10 10 10 10 10 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 12 12 16 16 mA mA Max., mA1 Max., mA1 A2 A2 2 4 6 8 2 4 6 8 11 22 44 44 9 17 35 35 10 10 10 10 10 10 10 10 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-9 * AC Loading v1.0 2 - 37 Automotive ProASIC3 DC and Switching Characteristics Table 2-56 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.8 Measuring Point* (V) 0.9 CLOAD (pF) 35 * Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points. Timing Characteristics Table 2-57 * 1.8 V LVCMOS High Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 13.26 11.28 7.73 6.58 4.97 4.23 4.39 3.73 3.95 3.36 3.95 3.36 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.36 1.16 1.36 1.16 1.36 1.16 1.36 1.16 1.36 1.16 1.36 1.16 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 10.22 8.69 6.55 5.58 4.67 3.98 4.39 3.74 1.95 1.95 1.95 1.95 tZH 13.26 11.28 7.73 6.58 4.97 4.23 4.39 3.73 1.68 1.68 1.68 1.68 tLZ 1.53 1.53 1.78 1.78 1.95 1.95 1.99 1.99 4.14 3.52 4.14 3.52 tHZ 0.90 0.90 1.54 1.54 1.83 1.83 1.91 1.91 4.56 3.88 4.56 3.88 tZLS 12.72 10.82 9.05 7.70 7.17 6.10 6.89 5.86 3.16 3.16 3.16 3.16 tZHS 15.764 13.41 10.232 8.704 7.472 6.356 6.888 5.859 2.915 2.918 2.915 2.918 Units ns ns ns ns ns ns ns ns ns ns ns ns 2 -3 8 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-58 * 1.8 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 17.36 14.77 11.71 9.96 9.00 7.66 8.39 7.14 8.15 6.94 8.15 6.94 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 15.78 13.42 11.64 9.90 9.17 7.80 8.54 7.27 8.09 6.88 8.09 6.88 tZH 17.36 14.77 11.71 9.96 8.77 7.46 8.16 6.94 8.15 6.94 8.15 6.94 tLZ 1.53 1.54 1.78 1.78 1.95 1.95 1.99 1.99 2.05 2.05 2.05 2.05 tHZ 0.87 0.87 1.48 1.48 1.77 1.77 1.85 1.85 2.14 2.14 2.14 2.14 tZLS 18.28 15.55 14.14 12.03 11.67 9.92 11.04 9.40 10.59 9.01 10.59 9.01 tZHS 19.864 16.897 14.214 12.091 11.267 9.585 10.66 9.068 10.654 9.063 10.654 9.063 Units ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-59 * 1.8 V LVCMOS High Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 13.26 11.28 7.73 6.58 4.97 4.23 4.39 3.73 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.36 1.16 1.36 1.16 1.36 1.16 1.36 1.16 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 9.75 8.30 6.13 5.21 4.29 3.65 4.29 3.65 tZH 12.67 10.78 7.25 6.17 4.54 3.86 4.54 3.86 tLZ 1.24 1.24 1.46 1.46 1.62 1.62 1.62 1.62 tHZ 0.82 0.83 1.41 1.41 1.68 1.68 1.68 1.68 tZLS 12.26 10.43 8.63 7.34 6.79 5.78 6.79 5.78 tZHS 15.17 12.905 9.749 8.293 7.039 5.987 7.039 5.987 Units ns ns ns ns ns ns ns ns v1.0 2 - 39 Automotive ProASIC3 DC and Switching Characteristics Table 2-60 * 1.8 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 17.36 14.77 11.71 9.96 9.00 7.66 8.39 7.14 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 15.09 12.84 10.88 9.26 8.47 7.21 8.47 7.21 tZH 16.55 14.08 11.07 9.41 8.18 6.96 8.18 6.96 tLZ 1.24 1.24 1.47 1.47 1.62 1.62 1.62 1.62 tHZ 0.79 0.79 1.35 1.35 1.62 1.62 1.62 1.62 tZLS 17.59 14.96 13.38 11.38 10.97 9.33 10.97 9.33 tZHS 19.052 16.207 13.567 11.541 10.685 9.089 10.685 9.089 Units ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-61 * 1.8 V LVCMOS High Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 12.83 10.92 7.48 6.36 4.81 4.09 4.25 3.61 3.82 3.25 3.82 3.25 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.32 1.12 1.32 1.12 1.32 1.12 1.32 1.12 1.32 1.12 1.32 1.12 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 9.88 8.41 6.34 5.39 4.52 3.85 4.25 3.61 1.89 1.89 1.89 1.89 tZH 12.83 10.92 7.48 6.36 4.81 4.09 4.25 3.61 1.63 1.63 1.63 1.63 tLZ 1.48 1.48 1.72 1.72 1.89 1.89 1.92 1.93 4.00 3.41 4.00 3.41 tHZ 0.87 0.87 1.49 1.49 1.77 1.77 1.85 1.85 4.41 3.75 4.41 3.75 tZLS 12.30 10.46 8.76 7.45 6.94 5.90 6.67 5.67 3.06 3.06 3.06 3.06 tZHS 15.25 12.97 9.90 8.42 7.23 6.15 6.66 5.67 2.82 2.82 2.82 2.82 Units ns ns ns ns ns ns ns ns ns ns ns ns 2 -4 0 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-62 * 1.8 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 16 mA STD -1 tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 16.80 14.29 11.33 9.64 8.71 7.41 8.12 6.90 7.89 6.71 7.89 6.71 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 15.27 12.99 11.26 9.58 8.87 7.54 8.27 7.03 7.83 6.66 7.83 6.66 tZH 16.80 14.29 11.33 9.64 8.48 7.22 7.89 6.72 7.89 6.71 7.89 6.71 tLZ 1.48 1.49 1.73 1.73 1.89 1.89 1.93 1.93 1.98 1.98 1.98 1.98 tHZ 0.84 0.84 1.43 1.43 1.72 1.72 1.79 1.79 2.07 2.07 2.07 2.07 tZLS 17.69 15.05 13.68 11.64 11.29 9.60 10.69 9.09 10.25 8.72 10.25 8.72 tZHS 19.22 16.35 13.75 11.70 10.90 9.27 10.31 8.77 10.31 8.77 10.31 8.77 Units ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-63 * 1.8 V LVCMOS High Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 12.83 10.92 7.48 6.36 4.81 4.09 4.25 3.61 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.32 1.12 1.32 1.12 1.32 1.12 1.32 1.12 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 9.44 8.03 5.93 5.04 4.15 3.53 4.15 3.53 tZH 12.26 10.43 7.01 5.97 4.39 3.74 4.39 3.74 tLZ 1.20 1.20 1.41 1.42 1.57 1.57 1.57 1.57 tHZ 0.80 0.80 1.36 1.37 1.63 1.63 1.63 1.63 tZLS 11.86 10.09 8.35 7.10 6.57 5.59 6.57 5.59 tZHS 14.68 12.49 9.43 8.02 6.81 5.79 6.81 5.79 Units ns ns ns ns ns ns ns ns v1.0 2 - 41 Automotive ProASIC3 DC and Switching Characteristics Table 2-64 * 1.8 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 16.80 14.29 11.33 9.64 8.71 7.41 8.12 6.90 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 14.60 12.42 10.53 8.96 8.19 6.97 8.19 6.97 tZH 16.01 13.62 10.71 9.11 7.92 6.74 7.92 6.74 tLZ 1.20 1.20 1.42 1.42 1.57 1.57 1.57 1.57 tHZ 0.77 0.77 1.31 1.31 1.57 1.57 1.57 1.57 tZLS 17.02 14.48 12.95 11.01 10.61 9.03 10.61 9.03 tZHS 18.43 15.68 13.13 11.17 10.34 8.79 10.34 8.79 Units ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-65 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.5 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. -0.3 -0.3 -0.3 -0.3 -0.3 VIL Max., V VIH Min., V Max., V 3.6 3.6 3.6 3.6 3.6 VOL Max., V VOH Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 4 6 8 2 4 6 8 16 33 39 55 55 13 25 32 66 66 10 10 10 10 10 10 10 10 10 10 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.25 * VCCI 0.75 * VCCI 0.25 * VCCI 0.75 * VCCI 0.25 * VCCI 0.75 * VCCI 0.25 * VCCI 0.75 * VCCI 0.25 * VCCI 0.75 * VCCI 12 12 2 -4 2 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-66 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS Drive Strength Min., V 2 mA 4 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. 3. Software default selection highlighted in gray. -0.3 -0.3 VIL Max., V VIH Min., V Max., V 3.6 3.6 VOL Max., V VOH Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 4 0 0 0 0 10 10 10 10 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.25 * VCCI 0.75 * VCCI 2 0.25 * VCCI 0.75 * VCCI 4 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-10 * AC Loading Table 2-67 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.5 Measuring Point* (V) 0.75 CLOAD (pF) 35 * Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points. v1.0 2 - 43 Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-68 * 1.5 V LVCMOS High Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-69 * 1.5 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 14.29 12.16 11.19 9.52 10.44 8.88 9.96 8.47 9.96 8.47 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 1.45 1.23 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 14.32 12.18 11.40 9.70 10.63 9.04 10.15 8.63 10.15 8.63 tZH 14.29 12.16 10.67 9.08 9.94 8.46 9.94 8.46 9.94 8.46 tLZ 1.88 1.88 2.07 2.07 2.12 2.12 2.18 2.19 2.18 2.19 tHZ 1.43 1.43 1.77 1.77 1.86 1.86 2.19 2.20 2.19 2.20 tZLS 16.82 14.31 13.90 11.82 13.13 11.17 12.65 10.76 12.65 10.76 tZHS 16.794 14.286 13.175 11.207 12.442 10.584 12.445 10.586 12.445 10.586 Units ns ns ns ns ns ns ns ns ns ns tDOUT 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 0.64 0.55 tDP 9.35 7.95 5.94 5.05 5.22 4.44 4.56 3.88 4.56 3.88 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.61 1.37 1.61 1.37 1.61 1.37 1.61 1.37 1.61 1.37 tEOUT 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 0.46 0.39 tZL 7.63 6.49 5.42 4.61 5.09 4.33 2.25 2.25 2.25 2.25 tZH 9.35 7.95 5.94 5.05 5.22 4.44 1.98 1.98 1.98 1.98 tLZ 1.87 1.87 2.07 2.07 2.11 2.11 4.41 3.75 4.41 3.75 tHZ 1.50 1.50 1.84 1.85 1.93 1.93 4.70 4.00 4.70 4.00 tZLS 10.13 8.62 7.92 6.74 7.59 6.45 3.46 3.46 3.46 3.46 tZHS 11.851 10.081 8.442 7.181 7.718 6.566 3.211 3.213 3.211 3.213 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -4 4 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-70 * 1.5 V LVCMOS High Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-71 * 1.5 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 tDOUT 0.64 0.55 0.64 0.55 tDP 13.51 11.49 10.38 8.83 tDIN 0.05 0.04 0.05 0.04 tPY 1.45 1.23 1.45 1.23 tEOUT 0.46 0.39 0.46 0.39 tZL 14.32 12.18 11.40 9.70 tZH 14.29 12.16 10.67 9.08 tLZ 1.88 1.88 2.07 2.07 tHZ 1.43 1.43 1.77 1.77 tZLS 16.82 14.31 13.90 11.82 tZHS 16.794 14.286 13.175 11.207 Units ns ns ns ns tDOUT 0.64 0.55 0.64 0.55 tDP 8.76 7.45 5.41 4.60 tDIN 0.05 0.04 0.05 0.04 tPY 1.59 1.35 1.59 1.35 tEOUT 0.46 0.39 0.46 0.39 tZL 7.63 6.49 5.42 4.61 tZH 9.35 7.95 5.94 5.05 tLZ 1.87 1.87 2.07 2.07 tHZ 1.50 1.50 1.84 1.85 tZLS 10.13 8.62 7.92 6.74 tZHS 11.851 10.081 8.442 7.181 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-72 * 1.5 V LVCMOS High Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 9.05 7.70 5.75 4.89 5.05 4.29 4.41 3.75 4.41 3.75 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.56 1.32 1.56 1.32 1.56 1.32 1.56 1.32 1.56 1.32 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 7.38 6.28 5.25 4.46 4.92 4.19 2.18 2.18 2.18 2.18 tZH 9.05 7.70 5.75 4.89 5.05 4.29 1.91 1.91 1.91 1.91 tLZ 1.81 1.81 2.00 2.00 2.04 2.04 4.27 3.63 4.27 3.63 tHZ 1.45 1.45 1.78 1.78 1.87 1.87 4.55 3.87 4.55 3.87 tZLS 9.80 8.34 7.67 6.52 7.34 6.24 3.35 3.35 3.35 3.35 tZHS 11.47 9.75 8.17 6.95 7.47 6.35 3.11 3.11 3.11 3.11 Units ns ns ns ns ns ns ns ns ns ns v1.0 2 - 45 Automotive ProASIC3 DC and Switching Characteristics Table 2-73 * 1.5 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 6 mA STD -1 8 mA STD -1 12 mA STD -1 tDOUT 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 0.63 0.53 tDP 13.83 11.76 10.83 9.21 10.10 8.59 9.64 8.20 9.64 8.20 tDIN 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 0.05 0.04 tPY 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 1.40 1.19 tEOUT 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 0.45 0.38 tZL 13.86 11.79 11.03 9.38 10.28 8.75 9.82 8.35 9.82 8.35 tZH 13.83 11.76 10.33 8.79 9.62 8.18 9.62 8.18 9.62 8.18 tLZ 1.82 1.82 2.00 2.01 2.05 2.05 2.11 2.11 2.11 2.11 tHZ 1.39 1.39 1.71 1.72 1.80 1.80 2.12 2.12 2.12 2.12 tZLS 16.28 13.85 13.45 11.44 12.70 10.81 12.23 10.41 12.23 10.41 tZHS 16.25 13.82 12.75 10.84 12.04 10.24 12.04 10.24 12.04 10.24 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-74 * 1.5 V LVCMOS High Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-75 * 1.5 V LVCMOS Low Slew Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade STD -1 4 mA STD -1 tDOUT 0.63 0.53 0.63 0.53 tDP 13.07 11.12 10.04 8.54 tDIN 0.05 0.04 0.05 0.04 tPY 1.40 1.19 1.40 1.19 tEOUT 0.45 0.38 0.45 0.38 tZL 13.86 11.79 11.03 9.38 tZH 13.83 11.76 10.33 8.79 tLZ 1.82 1.82 2.00 2.01 tHZ 1.39 1.39 1.71 1.72 tZLS 16.28 13.85 13.45 11.44 tZHS 16.25 13.82 12.75 10.84 Units ns ns ns ns tDOUT 0.63 0.53 0.63 0.53 tDP 8.47 7.21 5.24 4.45 tDIN 0.05 0.04 0.05 0.04 tPY 1.54 1.31 1.54 1.31 tEOUT 0.45 0.38 0.45 0.38 tZL 7.38 6.28 5.25 4.46 tZH 9.05 7.70 5.75 4.89 tLZ 1.81 1.81 2.00 2.00 tHZ 1.45 1.45 1.78 1.78 tZLS 9.80 8.34 7.67 6.52 tZHS 11.47 9.75 8.17 6.95 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -4 6 v1.0 Automotive ProASIC3 DC and Switching Characteristics 3.3 V PCI, 3.3 V PCI-X The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-76 * Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X Drive Strength Per PCI specification Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 125C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described in Figure 2-11. VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 A2 A2 Per PCI curves 10 10 R = 25 Test Point Datapath R to VCCI for tDP (F) R to GND for tDP (R) R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ Figure 2-11 * AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-77. Table 2-77 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 3.3 Measuring Point* (V) 0.285 * VCCI for tDP(R) 0.615 * VCCI for tDP(F) * Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points. CLOAD (pF) 10 Timing Characteristics Table 2-78 * 3.3 V PCI/PCI-X Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade Std. -1 tDOUT 0.64 0.55 tDP 2.58 2.19 tDIN 0.05 0.04 tPY 0.95 0.81 tEOUT 0.46 0.39 tZL 1.27 1.27 tZH 0.94 0.94 tLZ 3.12 2.65 tHZ 3.60 3.06 tZLS 2.49 2.49 tZHS 2.18 2.18 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 47 Automotive ProASIC3 DC and Switching Characteristics Table 2-79 * 3.3 V PCI/PCI-X Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade Std. -1 tDOUT 0.64 0.55 tDP 3.00 2.55 tDIN 0.05 0.04 tPY 0.93 0.79 tEOUT 0.46 0.39 tZL 1.27 1.27 tZH 0.94 0.94 tLZ 3.12 2.65 tHZ 3.60 3.06 tZLS 2.49 2.49 tZHS 2.18 2.18 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-80 * 3.3 V PCI/PCI-X Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade Std. -1 tDOUT 0.628 0.53 tDP 2.50 2.12 tDIN 0.05 0.04 tPY 0.92 0.78 tEOUT 0.45 0.38 tZL 1.23 1.23 tZH 0.91 0.91 tLZ 3.02 2.57 tHZ 3.48 2.96 tZLS 2.40 2.41 tZHS 2.11 2.11 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-81 * 3.3 V PCI/PCI-X Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade Std. -1 tDOUT 0.628 0.53 tDP 2.90 2.47 tDIN 0.05 0.04 tPY 0.90 0.77 tEOUT 0.45 0.38 tZL 1.23 1.23 tZH 0.91 0.91 tLZ 3.02 2.57 tHZ 3.48 2.96 tZLS 2.40 2.41 tZHS 2.11 2.11 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-12 on page 2-49. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes). 2 -4 8 v1.0 Automotive ProASIC3 DC and Switching Characteristics Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 Z0 = 50 140 N 165 Z0 = 50 100 N P FPGA + - INBUF_LVDS Figure 2-12 * LVDS Circuit Diagram and Board-Level Implementation Table 2-82 * Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH VI VODIFF VOCM VICM VIDIFF Notes: 1. 5% 2. Differential input voltage = 350 mV Table 2-83 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.075 Input HIGH (V) 1.325 Measuring Point* (V) Cross point Supply Voltage Output LOW Voltage Output HIGH Voltage Input Voltage Differential Output Voltage Output Common-Mode Voltage Input Common-Mode Voltage Input Differential Voltage Description Min. 2.375 0.9 1.25 0 250 1.125 0.05 100 Typ. 2.5 1.075 1.425 - 350 1.25 1.25 350 Max. 2.625 1.25 1.6 2.925 450 1.375 2.35 - Units V V V V mV V V mV * Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points. Timing Characteristics Table 2-84 * LVDS Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade Std. -1 tDOUT 0.64 0.55 tDP 2.05 1.74 tDIN 0.05 0.04 tPY 1.79 1.52 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 49 Automotive ProASIC3 DC and Switching Characteristics Table 2-85 * LVDS Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade Std. -1 tDOUT 0.63 0.53 tDP 1.98 1.68 tDIN 0.05 0.04 tPY 1.73 1.47 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-13. The input and output buffer delays are available in the LVDS section in Table 2-84 on page 2-49. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5"). Receiver EN Transceiver EN Driver Receiver EN EN Transceiver EN D + R + - T + - - R + - T + BIBUF_LVDS - RS Zstub Z0 RT Z 0 RS Zstub Zstub Z0 Z0 RS RS Zstub Zstub Z0 Z0 RS RS Zstub Zstub Z0 Z0 RS RS Zstub ... Z0 Z0 RS RS Z0 Z0 RT Figure 2-13 * B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-14 on page 2-51. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. 2 -5 0 v1.0 Automotive ProASIC3 DC and Switching Characteristics Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Z0 = 50 187 W N 100 Z0 = 50 100 N P FPGA + - INBUF_LVPECL Figure 2-14 * LVPECL Circuit Diagram and Board-Level Implementation Table 2-86 * Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH VIL, VIH VODIFF VOCM VICM VIDIFF Description Supply Voltage Output LOW Voltage Output HIGH Voltage Input LOW, Input HIGH Voltages Differential Output Voltage Output Common-Mode Voltage Input Common-Mode Voltage Input Differential Voltage 0.96 1.8 0 0.625 1.762 1.01 300 Min. 3.0 1.27 2.11 3.3 0.97 1.98 2.57 1.06 1.92 0 0.625 1.762 1.01 300 Max. Min. 3.3 1.43 2.28 3.6 0.97 1.98 2.57 1.30 2.13 0 0.625 1.762 1.01 300 Max. Min. 3.6 1.57 2.41 3.9 0.97 1.98 2.57 Max. Units V V V V V V V mV Table 2-87 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.64 Input HIGH (V) 1.94 Measuring Point* (V) Cross point * Measuring point = Vtrip. See Table 2-18 on page 2-17 for a complete table of trip points. Timing Characteristics Table 2-88 * LVPECL Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade Std. -1 tDOUT 0.64 0.55 tDP 2.01 1.71 tDIN 0.05 0.04 tPY 1.57 1.34 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-89 * LVPECL Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade Std. -1 tDOUT 0.63 0.53 tDP 1.95 1.66 tDIN 0.05 0.04 tPY 1.52 1.29 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 51 Automotive ProASIC3 DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L Pad Out D DOUT Data_out TRIBUF Data PRE D Q C DFN1E1P1 E B E Y Core Array F G PRE D Q DFN1E1P1 E INBUF INBUF Enable EOUT H I CLKBUF CLK A J K Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E CLKBUF INBUF INBUF Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered CLK Enable Figure 2-15 * Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset 2 -5 2 v1.0 D_Enable Automotive ProASIC3 DC and Switching Characteristics Table 2-90 * Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOPRE2Q tOREMPRE tORECPRE tOECLKQ tOESUD tOEHD tOESUE tOEHE tOEPRE2Q tOEREMPRE tOERECPRE tICLKQ tISUD tIHD tISUE tIHE tIPRE2Q tIREMPRE tIRECPRE Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Measuring Nodes (from, to)* H, DOUT F, H F, H G, H G, H L, DOUT L, H L, H H, EOUT J, H J, H K, H K, H I, EOUT I, H I, H A, E C, A C, A B, A B, A D, E D, A D, A * See Figure 2-15 on page 2-52 for more information. v1.0 2 - 53 Automotive ProASIC3 DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Pad Out DOUT Y D CC Q EE DFN1E1C1 E BB CLR LL CLKBUF Data Core Array Data_out FF TRIBUF INBUF INBUF D Q DFN1E1C1 GG E CLR EOUT Enable CLK HH AA JJ DD KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered INBUF CLR D Q DFN1E1C1 E CLR INBUF INBUF CLKBUF Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered Enable Figure 2-16 * Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear 2 -5 4 v1.0 D_Enable CLK Automotive ProASIC3 DC and Switching Characteristics Table 2-91 * Parameter Definitions and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOREMCLR tORECCLR tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEREMCLR tOERECCLR tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIREMCLR tIRECCLR Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Measuring Nodes (from, to)* HH, DOUT FF, HH FF, HH GG, HH GG, HH LL, DOUT LL, HH LL, HH HH, EOUT JJ, HH JJ, HH KK, HH KK, HH II, EOUT II, HH II, HH AA, EE CC, AA CC, AA BB, AA BB, AA DD, EE DD, AA DD, AA * See Figure 2-16 on page 2-54 for more information. v1.0 2 - 55 Automotive ProASIC3 DC and Switching Characteristics Input Register tICKMPWH tICKMPWL 50% 50% tISUD Data 1 50% 0 tIHD 50% 50% 50% 50% 50% 50% CLK Enable 50% tIHE 50% tIWPRE tISUE tIRECPRE 50% tIWCLR tIRECCLR 50% tIREMPRE 50% tIREMCLR 50% Preset Clear tIPRE2Q Out_1 50% tICLKQ 50% 50% tICLR2Q 50% Figure 2-17 * Input Register Timing Diagram Timing Characteristics Table 2-92 * Input Data Register Propagation Delays Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width HIGH for the Input Data Register Clock Minimum Pulse Width LOW for the Input Data Register -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.29 0.34 0.32 0.38 0.00 0.00 0.45 0.53 0.00 0.00 0.55 0.65 0.55 0.65 0.00 0.00 0.27 0.32 0.00 0.00 0.27 0.32 0.25 0.30 0.25 0.30 0.41 0.48 0.37 0.43 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -5 6 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-93 * Input Data Register Propagation Delays Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width HIGH for the Input Data Register Clock Minimum Pulse Width LOW for the Input Data Register -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.29 0.34 0.31 0.37 0.00 0.00 0.44 0.52 0.00 0.00 0.54 0.64 0.54 0.64 0.00 0.00 0.27 0.31 0.00 0.00 0.27 0.31 0.25 0.30 0.25 0.30 0.41 0.48 0.37 0.43 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Output Register tOCKMPWH tOCKMPWL 50% 50% tOSUD tOHD Data_out 1 50% 0 50% 50% 50% 50% 50% 50% CLK Enable 50% tOHE 50% tOWPRE tORECPRE 50% tORECCLR tOREMPRE 50% tOREMCLR 50% Preset tOSUE tOWCLR Clear tOPRE2Q DOUT 50% tOCLKQ 50% tOCLR2Q 50% 50% 50% Figure 2-18 * Output Register Timing Diagram v1.0 2 - 57 Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-94 * Output Data Register Propagation Delays Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width HIGH for the Output Data Register Clock Minimum Pulse Width LOW for the Output Data Register -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.72 0.84 0.38 0.45 0.00 0.00 0.53 0.63 0.00 0.00 0.98 1.15 0.98 1.15 0.00 0.00 0.27 0.32 0.00 0.00 0.27 0.32 0.25 0.30 0.25 0.30 0.41 0.48 0.37 0.43 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-95 * Output Data Register Propagation Delays Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width HIGH for the Output Data Register Clock Minimum Pulse Width LOW for the Output Data Register -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.70 0.82 0.37 0.44 0.00 0.00 0.52 0.61 0.00 0.00 0.96 1.12 0.96 1.12 0.00 0.00 0.27 0.31 0.00 0.00 0.27 0.31 0.25 0.30 0.25 0.30 0.41 0.48 0.37 0.43 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -5 8 v1.0 Automotive ProASIC3 DC and Switching Characteristics Output Enable Register tOECKMPWH tOECKMPWL 50% CLK 50% tOESUD tOEHD 50% 50% 50% 50% 50% D_Enable 1 50% 0 50% Enable 50% tOEWPRE 50% tOERECPRE 50% tOEREMPRE 50% Preset tOESUEtOEHE tOEWCLR 50% Clear tOEPRE2Q EOUT 50% tOECLKQ 50% tOECLR2Q 50% tOERECCLR 50% tOEREMCLR 50% Figure 2-19 * Output Enable Register Timing Diagram Timing Characteristics Table 2-96 * Output Enable Register Propagation Delays Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width LOW for the Output Enable Register -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.54 0.64 0.38 0.45 0.00 0.00 0.53 0.62 0.00 0.00 0.81 0.95 0.81 0.95 0.00 0.00 0.27 0.32 0.00 0.00 0.27 0.32 0.25 0.30 0.25 0.30 0.41 0.48 0.37 0.43 tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 59 Automotive ProASIC3 DC and Switching Characteristics Table 2-97 * Output Enable Register Propagation Delays Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width LOW for the Output Enable Register -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.53 0.62 0.37 0.44 0.00 0.00 0.52 0.61 0.00 0.00 0.79 0.93 0.79 0.93 0.00 0.00 0.27 0.31 0.00 0.00 0.27 0.31 0.25 0.30 0.25 0.30 0.41 0.48 0.37 0.43 tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -6 0 v1.0 Automotive ProASIC3 DC and Switching Characteristics DDR Module Specifications Input DDR Module Input DDR INBUF Data A FF1 D Out_QF (to core) CLK CLKBUF B FF2 E Out_QR (to core) CLR INBUF C DDR_IN Figure 2-20 * Input DDR Timing Model Table 2-98 * Parameter Definitions Parameter Name tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR Parameter Definition Clock-to-Out Out_QR Clock-to-Out Out_QF Data Setup Time of DDR Input Data Hold Time of DDR Input Clear-to-Out Out_QR Clear-to-Out Out_QF Clear Removal Clear Recovery Measuring Nodes (from, to) B, D B, E A, B A, B C, D C, E C, B C, B v1.0 2 - 61 Automotive ProASIC3 DC and Switching Characteristics CLK tDDRISUD Data 1 2 3 4 5 6 7 tDDRIHD 8 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF tDDRICLR2Q2 Out_QR 3 2 4 tDDRICLKQ2 5 7 6 9 Figure 2-21 * Input DDR Timing Diagram Timing Characteristics Table 2-99 * Input DDR Propagation Delays Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR Data Hold for Input DDR Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal Time for Input DDR Asynchronous Clear Recovery Time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width HIGH for Input DDR Clock Minimum Pulse Width LOW for Input DDR Maximum Frequency for Input DDR -1 0.33 0.47 0.34 0.00 0.56 0.69 0.00 0.27 0.25 0.41 0.37 TBD Std. 0.39 0.56 0.40 0.00 0.66 0.82 0.00 0.32 0.30 0.48 0.43 TBD Units ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -6 2 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-100 * Input DDR Propagation Delays Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR Data Hold for Input DDR Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal Time for Input DDR Asynchronous Clear Recovery Time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width HIGH for Input DDR Clock Minimum Pulse Width LOW for Input DDR Maximum Frequency for Input DDR -1 0.33 0.46 0.34 0.00 0.55 0.68 0.00 0.27 0.25 0.41 0.37 TBD Std. 0.38 0.54 0.40 0.00 0.65 0.80 0.00 0.31 0.30 0.48 0.43 TBD Units ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Output DDR Module Output DDR Data_F (from core) A X FF1 B Out X 0 E X X FF2 1 X OUTBUF CLK CLKBUF C D Data_R (from core) CLR INBUF B C X X DDR_OUT Figure 2-22 * Output DDR Timing Model v1.0 2 - 63 Automotive ProASIC3 DC and Switching Characteristics Table 2-101 * Parameter Definitions Parameter Name tDDROCLKQ tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 Clock-to-Out Asynchronous Clear-to-Out Clear Removal Clear Recovery Data Setup Data_F Data Setup Data_R Data Hold Data_F Data Hold Data_R Parameter Definition Measuring Nodes (from, to) B, E C, E C, B C, B A, B D, B A, B D, B CLK tDDROSUD2 tDDROHD2 Data_F 1 2 tDDROREMCLR Data_R 6 7 tDDROHD1 8 9 10 tDDRORECCLR CLR tDDROREMCLR tDDROCLR2Q Out tDDROCLKQ 7 2 8 3 9 4 10 11 3 4 5 Figure 2-23 * Output DDR Timing Diagram 2 -6 4 v1.0 Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-102 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter tDDROCLKQ tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width HIGH for the Output DDR Clock Minimum Pulse Width LOW for the Output DDR Maximum Frequency for the Output DDR -1 0.85 0.46 0.46 0.00 0.00 0.97 0.00 0.27 0.25 0.41 0.37 TBD Std. 1.00 0.54 0.54 0.00 0.00 1.15 0.00 0.32 0.30 0.48 0.43 TBD Units ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-103 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Parameter tDDROCLKQ tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width HIGH for the Output DDR Clock Minimum Pulse Width LOW for the Output DDR Maximum Frequency for the Output DDR -1 0.84 0.45 0.45 0.00 0.00 0.96 0.00 0.27 0.25 0.41 0.37 TBD Std. 0.98 0.53 0.53 0.00 0.00 1.12 0.00 0.31 0.30 0.48 0.43 TBD Units ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 65 Automotive ProASIC3 DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. A INV Y A OR2 B A AND2 B Y Y A NOR2 B Y A NAND2 B A B C Y A B XOR2 Y XOR3 Y A A B C B C MAJ3 Y A 0 MUX2 B 1 Y NAND3 S Figure 2-24 * Sample of Combinatorial Cells 2 -6 6 v1.0 Automotive ProASIC3 DC and Switching Characteristics tPD A NAND2 or Any Combinatorial Logic Y B tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC 50% A, B, C 50% GND VCC 50% OUT GND VCC OUT 50% tPD (RF) Figure 2-25 * Timing Model and Waveforms 50% tPD (RR) tPD (FF) tPD (FR) GND 50% v1.0 2 - 67 Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-104 * Combinatorial Cell Propagation Delays Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Y = !A Y=A*B Y = !(A * B) Y=A+B Y = !(A + B) Y=AB Y = MAJ(A , B, C) Y=ABC Y = A !S + B S Y=A*B*C Equation Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD -1 0.49 0.57 0.57 0.59 0.59 0.90 0.85 1.06 0.62 0.68 Std. 0.57 0.67 0.67 0.69 0.69 1.05 1.00 1.25 0.72 0.80 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-105 * Combinatorial Cell Propagation Delays Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Y = !A Y=A*B Y = !(A * B) Y=A+B Y = !(A + B) Y=AB Y = MAJ(A , B, C) Y=ABC Y = A !S + B S Y=A*B*C Equation Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD -1 0.48 0.56 0.56 0.58 0.58 0.88 0.83 1.04 0.60 0.67 Std. 0.56 0.66 0.66 0.68 0.68 1.03 0.98 1.23 0.71 0.79 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -6 8 v1.0 Automotive ProASIC3 DC and Switching Characteristics VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e and ProASIC3/E Macro Library Guide. Data D DFN1 Q Out Data D En CLK Q DFN1E1 Out CLK PRE Data D Q DFN1C1 Out Data En CLK D Q Out DFI1E1P1 CLK CLR Figure 2-26 * Sample of Sequential Cells v1.0 2 - 69 Automotive ProASIC3 DC and Switching Characteristics tCKMPWH tCKMPWL 50% 50% tSUD Data 50% tHD 0 50% 50% 50% 50% 50% 50% CLK EN 50% tHE tWPRE tSUE 50% tRECPRE 50% tRECCLR 50% tREMPRE 50% tREMCLR 50% PRE tWCLR CLR tPRE2Q Out tCLKQ 50% 50% 50% tCLR2Q 50% Figure 2-27 * Timing Model and Waveforms Timing Characteristics Table 2-106 * Register Delays Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width HIGH for the Core Register Clock Minimum Pulse Width LOW for the Core Register Description -1 0.67 0.52 0.00 0.55 0.00 0.49 0.49 0.00 0.27 0.00 0.27 0.25 0.25 0.41 0.37 Std. 0.79 0.61 0.00 0.65 0.00 0.57 0.57 0.00 0.32 0.00 0.32 0.30 0.30 0.48 0.43 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -7 0 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-107 * Register Delays Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width HIGH for the Core Register Clock Minimum Pulse Width LOW for the Core Register Description -1 0.66 0.51 0.00 0.54 0.00 0.48 0.48 0.00 0.27 0.00 0.27 0.25 0.25 0.41 0.37 Std. 0.77 0.60 0.00 0.64 0.00 0.56 0.56 0.00 0.31 0.00 0.31 0.30 0.30 0.48 0.43 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 71 Automotive ProASIC3 DC and Switching Characteristics Global Resource Characteristics A3P250 Clock Tree Topology Clock delays are device-specific. Figure 2-28 is an example of a global tree used for clock routing. The global tree presented in Figure 2-28 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-28 * Example of Global Tree Use in an A3P250 Device for Clock Routing 2 -7 2 v1.0 Automotive ProASIC3 DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard-dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-77. Table 2-114 on page 2-76 to Table 2-125 on page 2-95 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-108 * A3P060 Global Resource Commercial-Case Conditions: TJ = 135C, VCC = 1.425 V -1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-109 * A3P060 Global Resource Commercial-Case Conditions: TJ = 115C, VCC = 1.425 V -1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.34 0.40 Min. 1 Std. 2 Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock Min. 1 Max. Min. 1 Max.2 1.37 1.42 Units ns ns ns ns 0.87 0.86 1.16 1.20 1.02 1.01 0.35 0.41 ns MHz Std. Min.1 1.00 0.99 Max.2 1.33 1.38 Units ns ns ns ns ns MHz Max.2 1.13 1.18 0.85 0.84 v1.0 2 - 73 Automotive ProASIC3 DC and Switching Characteristics Table 2-110 * A3P125 Global Resource Commercial-Case Conditions: TJ = 135C, VCC = 1.425 V -1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-111 * A3P125 Global Resource Commercial-Case Conditions: TJ = 115C, VCC = 1.425 V -1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.34 0.40 Min. 1 Std. 2 Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock Min. 1 Max. Min. 1 Max.2 1.43 1.49 Units ns ns ns ns 0.93 0.92 1.22 1.26 1.09 1.08 0.35 0.41 ns MHz Std. Min.1 1.06 1.05 Max.2 1.40 1.45 Units ns ns ns ns ns MHz Max.2 1.19 1.23 0.90 0.90 2 -7 4 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-112 * A3P250 Global Resource Commercial-Case Conditions: TJ = 135C, VCC = 1.425 V -1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-113 * A3P250 Global Resource Commercial-Case Conditions: TJ = 115C, VCC = 1.425 V -1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.34 0.40 Min. 1 Std. 2 Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock Min. 1 Max. Min. 1 Max.2 1.47 1.51 Units ns ns ns ns 0.96 0.94 1.25 1.28 1.13 1.10 0.35 0.41 ns MHz Std. Min.1 1.10 1.08 Max.2 1.44 1.47 Units ns ns ns ns ns MHz Max.2 1.22 1.25 0.94 0.92 v1.0 2 - 75 Automotive ProASIC3 DC and Switching Characteristics Table 2-114 * A3P1000 Global Resource Automotive-Case Conditions: TJ = 135C, VCC = 1.425 V -1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Table 2-115 * A3P1000 Global Resource Automotive-Case Conditions: TJ = 115C, VCC = 1.425 V -1 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.34 0.40 Min. 1 Std. 2 Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock Min. 1 Max. Min. 1 Max.2 1.72 1.76 Units ns ns ns ns 1.17 1.15 1.46 1.50 1.37 1.36 0.35 0.41 ns MHz Std. Min.1 1.34 1.32 Max.2 1.68 1.72 Units ns ns ns ns ns MHz Max.2 1.43 1.46 1.14 1.13 2 -7 6 v1.0 Automotive ProASIC3 DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-116 * Automotive ProASIC3 CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Input Period Jitter CCC Output Peak-to-Peak Period Jitter FCCC_OUT 1 Global Network Used 0.75 MHz to 24 MHz 24 MHz to 100 MHz 100 MHz to 250 MHz 250 MHz to 350 MHz Acquisition Time (A3P250 and A3P1000 only) (all other dies) Tracking Jitter4 (A3P250 and A3P1000 only) (all other dies) Output Duty Cycle Delay Range in Block: Programmable Delay Delay Range in Block: Fixed Delay Notes: 1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-5 for deratings. 2. TJ = 25C, VCC = 1.5 V 3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 1, 2 Minimum 1.5 0.75 Typical Maximum 350 350 Units MHz MHz ps Blocks1, 2 160 32 1.5 Max Peak-to-Peak Period Jitter 3 Global Networks Used 0.70% 1.20% 2.00% 5.60% 300 300 300 6.0 1.6 1.6 1.6 0.8 48.5 51.5 5.56 5.56 2.2 0.6 0.025 Number of Programmable Values in Each Programmable Delay Block ns 0.50% 1.00% 1.75% 2.50% LockControl = 0 LockControl = 1 LockControl = 0 LockControl = 1 LockControl = 0 LockControl = 1 LockControl = 0 LockControl = 1 11, 2 s s s ms ns ns ns ns % ns ns ns Delay Range in Block: Programmable Delay 21, 2 v1.0 2 - 77 Automotive ProASIC3 DC and Switching Characteristics Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min. Figure 2-29 * Peak-to-Peak Jitter Definition 2 -7 8 v1.0 Automotive ProASIC3 DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0 RAM512x18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 FIFO4K18 RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY DINA0 RW1 RW0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0 PIPE AEVAL0 AFVAL11 AFVAL10 REN RCLK WADDR8 WADDR7 AFVAL0 REN RBLK RCLK WD17 WD16 WADDR0 WD17 WD16 WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0 WD0 WEN WBLK WCLK RPIPE WEN WCLK RESET RESET Figure 2-30 * RAM Models v1.0 2 - 79 Automotive ProASIC3 DC and Switching Characteristics Timing Waveforms tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tCKQ1 DO Dn D0 tDOH1 Figure 2-31 * RAM Read for Pass-Through Output tCKL tAH A1 A2 tBKH tENH D1 D2 tCYC tCKH CLK t ADD tBKS BLK_B tENS WEN_B tCKQ2 DO Dn D0 tDOH2 Figure 2-32 * RAM Read for Pipelined Output AS tCKL tAH A0 A1 A2 tBKH tENH D1 2 -8 0 v1.0 Automotive ProASIC3 DC and Switching Characteristics tCYC tCKH CLK tAS ADD tBKS tBKH BLK_B tENS WEN_B tDS DI DI0 tDH DI1 tENH A0 tAH A1 A2 tCKL DO Dn D2 Figure 2-33 * RAM Write, Output Retained (WMODE = 0) tCYC tCKH CLK tAS ADD tBKS BLK_B tENS WEN_B tDS DI DO (pass-through) DO (pipelined) DI0 tDH DI1 DI2 tBKH A0 tAH A1 A2 tCKL Dn DI0 DI1 Dn DI0 DI1 Figure 2-34 * RAM Write, Output as Write Data (WMODE = 1) v1.0 2 - 81 Automotive ProASIC3 DC and Switching Characteristics CLK1 tAS ADD1 tDS DI1 tAH A0 tDH D1 tCCKH CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) A0 D0 tCKQ1 Dn D0 tCKQ2 Dn D0 A1 D2 A3 D3 tAS tAH A0 A4 D4 Figure 2-35 * Write Access after Write to Same Address 2 -8 2 v1.0 Automotive ProASIC3 DC and Switching Characteristics CLK1 tAS tAH ADD1 DI1 CLK2 WEN_B1 WEN_B2 tAS tAH ADD2 DO2 (pass-through) DO2 (pipelined) Dn Dn A0 tCKQ1 D0 tCKQ2 D0 D1 A1 A4 A0 tDS tDH D0 tWRO A2 D2 A3 D3 Figure 2-36 * Read Access after Write to Same Address v1.0 2 - 83 Automotive ProASIC3 DC and Switching Characteristics CLK1 tAS ADD1 WEN_B1 tCKQ1 DO1 (pass-through) DO1 (pipelined) CLK2 tAS ADD2 A0 D1 tAH A1 D2 A3 D3 Dn D0 tCKQ2 Dn tCCKH D0 tCKQ1 D1 tAH A0 A1 A0 DI2 WEN_B2 Figure 2-37 * Write Access after Read to Same Address tCYC tCKH CLK tCKL RESET_B tRSTBQ DO Dm Dn Figure 2-38 * RAM Reset 2 -8 4 v1.0 Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-117 * RAM4K9 Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter Description tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 Address Setup Time Address Hold Time REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) Clock HIGH to New Data Valid on DO (flow-through, WMODE = 1) tCKQ2 tWRO tCCKH tRSTBQ Clock HIGH to New Data Valid on DO (pipelined) -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 0.30 0.36 0.00 0.00 0.17 0.20 0.12 0.14 0.28 0.33 0.02 0.03 0.22 0.26 0.00 0.00 2.17 2.55 2.86 3.37 1.09 1.28 Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) 1.12 1.32 1.12 1.32 0.35 0.41 1.82 2.14 0.26 0.30 3.93 4.62 255 217 tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 85 Automotive ProASIC3 DC and Switching Characteristics Table 2-118 * RAM512X18 Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address Setup Time Address Hold Time REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time Input data (DI) Setup Time Input data (DI) Hold Time Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) Clock HIGH to New Data Valid on DO (pipelined) Description -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 0.30 0.35 0.00 0.00 0.11 0.13 0.07 0.08 0.22 0.26 0.00 0.00 2.58 3.03 1.07 1.26 Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency 1.10 1.29 1.10 1.29 0.34 0.40 1.79 2.10 0.25 0.30 3.85 4.53 260 221 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -8 6 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-119 * RAM4K9 Automotive-Case Conditions: TJ = 115C, Worst Case VCC = 1.425 V Parameter Description tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 Address Setup Time Address Hold Time REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input data (DI) Setup Time Input data (DI) Hold Time Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) Clock HIGH to New Data Valid on DO (flow-through, WMODE = 1) tCKQ2 tWRO tCCKH tRSTBQ Clock HIGH to New Data Valid on DO (pipelined) -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 0.30 0.35 0.00 0.00 0.17 0.20 0.12 0.14 0.28 0.33 0.02 0.03 0.22 0.26 0.00 0.00 2.13 2.50 2.81 3.30 1.07 1.25 Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) 1.10 1.29 1.10 1.29 0.34 0.40 1.79 2.10 0.25 0.30 3.85 4.53 260 221 tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency Note: For specific junction temperature and voltage-supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 87 Automotive ProASIC3 DC and Switching Characteristics Table 2-120 * RAM512X18 Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address Setup Time Address Hold Time REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time Input data (DI) Setup Time Input data (DI) Hold Time Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) Clock HIGH to New Data Valid on DO (pipelined) Description -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 0.30 0.35 0.00 0.00 0.11 0.13 0.07 0.08 0.22 0.26 0.00 0.00 2.58 3.03 1.07 1.26 Address collision clk-to-clk delay for reliable read access after write on same TBD TBD address Address collision clk-to-clk delay for reliable write access after write/read on TBD TBD same address RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency 1.10 1.29 1.10 1.29 0.34 0.40 1.79 2.10 0.25 0.30 3.85 4.53 260 221 Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -8 8 v1.0 Automotive ProASIC3 DC and Switching Characteristics FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-39 * FIFO Model v1.0 2 - 89 Automotive ProASIC3 DC and Switching Characteristics Timing Waveforms RCLK/ WCLK tMPWRSTB RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) Figure 2-40 * FIFO Reset tRSTCK MATCH (A0) tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 2-41 * FIFO EMPTY Flag and AEMPTY Flag Assertion 2 -9 0 v1.0 Automotive ProASIC3 DC and Switching Characteristics tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-42 * FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA (Address Counter) MATCH (EMPTY) NO MATCH NO MATCH 2nd Rising Edge After 1st Write tRCKEF NO MATCH NO MATCH Dist = AEF_TH + 1 RCLK 1st Rising Edge After 1st Write EMPTY tCKAF AEMPTY Figure 2-43 * FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) NO MATCH (Address Counter) 1st Rising Edge After 1st WCLK Read FULL tCKAF AFULL NO MATCH 1st Rising Edge After 2nd Read tWCKF NO MATCH NO MATCH Dist = AFF_TH - 1 Figure 2-44 * FIFO FULL Flag and AFULL Flag Deassertion v1.0 2 - 91 Automotive ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-121 * FIFO Worst-Case Automotive Conditions: TJ = 135C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (flow-through) Clock HIGH to New Data Valid on DO (pipelined) RCLK HIGH to Empty Flag Valid WCLK HIGH to Full Flag Valid Clock HIGH to Almost Empty/Full Flag Valid RESET_B LOW to Empty/Full Flag Valid RESET_B LOW to Almost Empty/Full Flag Valid RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO -1 1.97 0.03 0.28 0.00 0.26 0.00 3.37 1.28 2.45 2.33 8.85 2.42 8.76 1.32 1.32 0.41 2.14 0.30 4.62 217 Std. 1.67 0.02 0.32 0.00 0.22 0.00 2.86 1.09 2.09 1.98 7.53 2.06 7.45 1.12 1.12 0.35 1.82 0.26 3.93 255 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. 2 -9 2 v1.0 Automotive ProASIC3 DC and Switching Characteristics Table 2-122 * FIFO Worst-Case Automotive Conditions: TJ = 115C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (flow-through) Clock HIGH to New Data Valid on DO (pipelined) RCLK HIGH to Empty Flag Valid WCLK HIGH to Full Flag Valid Clock HIGH to Almost Empty/Full Flag Valid RESET_B LOW to Empty/Full Flag Valid RESET_B LOW to Almost Empty/Full Flag Valid RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO -1 1.93 0.03 0.27 0.00 0.26 0.00 3.30 1.25 2.41 2.29 8.68 2.37 8.59 1.29 1.29 0.40 2.10 0.30 4.53 221 Std. 1.64 0.02 0.32 0.00 0.22 0.00 2.81 1.07 2.05 1.95 7.38 2.02 7.30 1.10 1.10 0.34 1.79 0.25 3.85 260 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. v1.0 2 - 93 Automotive ProASIC3 DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tHOLD tSU tHOLD tSU tHOLD Address A0 tCKQ2 A1 tCKQ2 D0 tCKQ2 D1 Data D0 Figure 2-45 * Timing Diagram Timing Characteristics Table 2-123 * Embedded FlashROM Access Time Automotive-Case Conditions: TJ = 135C, Worst-Case VCC = 1.425 V Parameter tSU tHOLD tCK2Q FMAX Description Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency -1 0.65 0.00 19.73 15 Std. 0.76 0.00 23.20 15 Units ns ns ns MHz Table 2-124 * Embedded FlashROM Access Time Automotive-Case Conditions: TJ = 115C, Worst-Case VCC = 1.425 V Parameter tSU tHOLD tCK2Q FMAX Description Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency -1 0.64 0.00 19.35 15 Std. 0.75 0.00 22.74 15 Units ns ns ns MHz 2 -9 4 v1.0 Automotive ProASIC3 DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-12 for more details. Timing Characteristics Table 2-125 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse 20 20 20 -2 -1 Std. Units ns ns ns ns ns ns MHz ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. Part Number and Revision Date Part Number 51700099-002-0 Revised January 2008 Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advanced status datasheet may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v1.0 2 - 95 Automotive ProASIC(R)3 Packaging 3 - Package Pin Assignments 100-Pin VQFP 100 1 100-Pin VQFP Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.0 3-1 Package Pin Assignments 100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A3P060 Function GND GAA2/IO51RSB1 IO52RSB1 GAB2/IO53RSB1 IO95RSB1 GAC2/IO94RSB1 IO93RSB1 IO92RSB1 GND GFB1/IO87RSB1 GFB0/IO86RSB1 VCOMPLF GFA0/IO85RSB1 VCCPLF GFA1/IO84RSB1 GFA2/IO83RSB1 VCC VCCIB1 GEC1/IO77RSB1 GEB1/IO75RSB1 GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 VMV1 GNDQ GEA2/IO71RSB1 GEB2/IO70RSB1 GEC2/IO69RSB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 100-Pin VQFP Pin Number 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A3P060 Function IO62RSB1 IO61RSB1 VCC GND VCCIB1 IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 GDC2/IO56RSB1 GDB2/IO55RSB1 GDA2/IO54RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO49RSB0 GDC0/IO46RSB0 GDC1/IO45RSB0 GCC2/IO43RSB0 GCB2/IO42RSB0 GCA0/IO40RSB0 GCA1/IO39RSB0 GCC0/IO36RSB0 GCC1/IO35RSB0 VCCIB0 GND VCC 100-Pin VQFP Pin Number 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P060 Function IO31RSB0 GBC2/IO29RSB0 GBB2/IO27RSB0 IO26RSB0 GBA2/IO25RSB0 VMV0 GNDQ GBA1/IO24RSB0 GBA0/IO23RSB0 GBB1/IO22RSB0 GBB0/IO21RSB0 GBC1/IO20RSB0 GBC0/IO19RSB0 IO18RSB0 IO17RSB0 IO15RSB0 IO13RSB0 IO11RSB0 VCCIB0 GND VCC IO10RSB0 IO09RSB0 IO08RSB0 GAC1/IO07RSB0 GAC0/IO06RSB0 GAB1/IO05RSB0 GAB0/IO04RSB0 GAA1/IO03RSB0 GAA0/IO02RSB0 IO01RSB0 IO00RSB0 3 -2 v1.0 Automotive ProASIC3 Packaging 100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A3P250 Function GND GAA2/IO118UDB3 IO118VDB3 GAB2/IO117UDB3 IO117VDB3 GAC2/IO116UDB3 IO116VDB3 IO112PSB3 GND GFB1/IO109PDB3 GFB0/IO109NDB3 VCOMPLF GFA0/IO108NPB3 VCCPLF GFA1/IO108PPB3 GFA2/IO107PSB3 VCC VCCIB3 GFC2/IO105PSB3 GEC1/IO100PDB3 GEC0/IO100NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 VMV3 GNDQ GEA2/IO97RSB2 GEB2/IO96RSB2 GEC2/IO95RSB2 IO93RSB2 IO92RSB2 IO91RSB2 IO90RSB2 IO88RSB2 IO86RSB2 100-Pin VQFP Pin Number 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A3P250 Function IO85RSB2 IO84RSB2 VCC GND VCCIB2 IO77RSB2 IO74RSB2 IO71RSB2 GDC2/IO63RSB2 GDB2/IO62RSB2 GDA2/IO61RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP NC TDO TRST VJTAG GDA1/IO60USB1 GDC0/IO58VDB1 GDC1/IO58UDB1 IO52NDB1 GCB2/IO52PDB1 GCA1/IO50PDB1 GCA0/IO50NDB1 GCC0/IO48NDB1 GCC1/IO48PDB1 VCCIB1 GND VCC 100-Pin VQFP Pin Number 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P250 Function IO43NDB1 GBC2/IO43PDB1 GBB2/IO42PSB1 IO41NDB1 GBA2/IO41PDB1 VMV1 GNDQ GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO29RSB0 IO27RSB0 IO25RSB0 IO23RSB0 IO21RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0 v1.0 3-3 Package Pin Assignments 144-Pin FBGA A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -4 v1.0 Automotive ProASIC3 Packaging 144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P060 Function GNDQ VMV0 GAB0/IO04RSB0 GAB1/IO05RSB0 IO08RSB0 GND IO11RSB0 VCC IO16RSB0 GBA0/IO23RSB0 GBA1/IO24RSB0 GNDQ GAB2/IO53RSB1 GND GAA0/IO02RSB0 GAA1/IO03RSB0 IO00RSB0 IO10RSB0 IO12RSB0 IO14RSB0 GBB0/IO21RSB0 GBB1/IO22RSB0 GND VMV0 IO95RSB1 GFA2/IO83RSB1 GAC2/IO94RSB1 VCC IO01RSB0 IO09RSB0 IO13RSB0 IO15RSB0 IO17RSB0 GBA2/IO25RSB0 IO26RSB0 GBC2/IO29RSB0 144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P060 Function IO91RSB1 IO92RSB1 IO93RSB1 GAA2/IO51RSB1 GAC0/IO06RSB0 GAC1/IO07RSB0 GBC0/IO19RSB0 GBC1/IO20RSB0 GBB2/IO27RSB0 IO18RSB0 IO28RSB0 GCB1/IO37RSB0 VCC GFC0/IO88RSB1 GFC1/IO89RSB1 VCCIB1 IO52RSB1 VCCIB0 VCCIB0 GCC1/IO35RSB0 VCCIB0 VCC GCA0/IO40RSB0 IO30RSB0 GFB0/IO86RSB1 VCOMPLF GFB1/IO87RSB1 IO90RSB1 GND GND GND GCC0/IO36RSB0 GCB0/IO38RSB0 GND GCA1/IO39RSB0 GCA2/IO41RSB0 144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P060 Function GFA1/IO84RSB1 GND VCCPLF GFA0/IO85RSB1 GND GND GND GDC1/IO45RSB0 IO32RSB0 GCC2/IO43RSB0 IO31RSB0 GCB2/IO42RSB0 VCC GFB2/IO82RSB1 GFC2/IO81RSB1 GEC1/IO77RSB1 VCC IO34RSB0 IO44RSB0 GDB2/IO55RSB1 GDC0/IO46RSB0 VCCIB0 IO33RSB0 VCC GEB1/IO75RSB1 IO78RSB1 VCCIB1 GEC0/IO76RSB1 IO79RSB1 IO80RSB1 VCC TCK GDA2/IO54RSB1 TDO GDA1/IO49RSB0 GDB1/IO47RSB0 v1.0 3-5 Package Pin Assignments 144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P060 Function GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 GEA2/IO71RSB1 IO65RSB1 IO64RSB1 GND IO57RSB1 GDC2/IO56RSB1 GND GDA0/IO50RSB0 GDB0/IO48RSB0 GND VMV1 GEB2/IO70RSB1 IO67RSB1 VCCIB1 IO62RSB1 IO59RSB1 IO58RSB1 TMS VJTAG VMV1 TRST GNDQ GEC2/IO69RSB1 IO68RSB1 IO66RSB1 IO63RSB1 IO61RSB1 IO60RSB1 NC TDI VCCIB1 VPUMP GNDQ 3 -6 v1.0 Automotive ProASIC3 Packaging 144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P125 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO11RSB0 GND IO18RSB0 VCC IO25RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GNDQ GAB2/IO69RSB1 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO08RSB0 IO14RSB0 IO19RSB0 IO22RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GND VMV0 IO132RSB1 GFA2/IO120RSB1 GAC2/IO131RSB1 VCC IO10RSB0 IO12RSB0 IO21RSB0 IO24RSB0 IO27RSB0 GBA2/IO41RSB0 IO42RSB0 GBC2/IO45RSB0 144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P125 Function IO128RSB1 IO129RSB1 IO130RSB1 GAA2/IO67RSB1 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO35RSB0 GBC1/IO36RSB0 GBB2/IO43RSB0 IO28RSB0 IO44RSB0 GCB1/IO53RSB0 VCC GFC0/IO125RSB1 GFC1/IO126RSB1 VCCIB1 IO68RSB1 VCCIB0 VCCIB0 GCC1/IO51RSB0 VCCIB0 VCC GCA0/IO56RSB0 IO46RSB0 GFB0/IO123RSB1 VCOMPLF GFB1/IO124RSB1 IO127RSB1 GND GND GND GCC0/IO52RSB0 GCB0/IO54RSB0 GND GCA1/IO55RSB0 GCA2/IO57RSB0 144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P125 Function GFA1/IO121RSB1 GND VCCPLF GFA0/IO122RSB1 GND GND GND GDC1/IO61RSB0 IO48RSB0 GCC2/IO59RSB0 IO47RSB0 GCB2/IO58RSB0 VCC GFB2/IO119RSB1 GFC2/IO118RSB1 GEC1/IO112RSB1 VCC IO50RSB0 IO60RSB0 GDB2/IO71RSB1 GDC0/IO62RSB0 VCCIB0 IO49RSB0 VCC GEB1/IO110RSB1 IO115RSB1 VCCIB1 GEC0/IO111RSB1 IO116RSB1 IO117RSB1 VCC TCK GDA2/IO70RSB1 TDO GDA1/IO65RSB0 GDB1/IO63RSB0 v1.0 3-7 Package Pin Assignments 144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P125 Function GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 GEA2/IO106RSB1 IO100RSB1 IO98RSB1 GND IO73RSB1 GDC2/IO72RSB1 GND GDA0/IO66RSB0 GDB0/IO64RSB0 GND VMV1 GEB2/IO105RSB1 IO102RSB1 VCCIB1 IO95RSB1 IO85RSB1 IO74RSB1 TMS VJTAG VMV1 TRST GNDQ GEC2/IO104RSB1 IO103RSB1 IO101RSB1 IO97RSB1 IO94RSB1 IO86RSB1 IO75RSB1 TDI VCCIB1 VPUMP GNDQ 3 -8 v1.0 Automotive ProASIC3 Packaging 144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P250 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO16RSB0 GND IO29RSB0 VCC IO33RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GNDQ GAB2/IO117UDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO14RSB0 IO19RSB0 IO22RSB0 IO30RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GND VMV1 IO117VDB3 GFA2/IO107PPB3 GAC2/IO116UDB3 VCC IO12RSB0 IO17RSB0 IO24RSB0 IO31RSB0 IO34RSB0 GBA2/IO41PDB1 IO41NDB1 GBC2/IO43PPB1 144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P250 Function IO112NDB3 IO112PDB3 IO116VDB3 GAA2/IO118UPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO35RSB0 GBC1/IO36RSB0 GBB2/IO42PDB1 IO42NDB1 IO43NPB1 GCB1/IO49PPB1 VCC GFC0/IO110NDB3 GFC1/IO110PDB3 VCCIB3 IO118VPB3 VCCIB0 VCCIB0 GCC1/IO48PDB1 VCCIB1 VCC GCA0/IO50NDB1 IO51NDB1 GFB0/IO109NPB3 VCOMPLF GFB1/IO109PPB3 IO107NPB3 GND GND GND GCC0/IO48NDB1 GCB0/IO49NPB1 GND GCA1/IO50PDB1 GCA2/IO51PDB1 144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P250 Function GFA1/IO108PPB3 GND VCCPLF GFA0/IO108NPB3 GND GND GND GDC1/IO58UPB1 IO53NDB1 GCC2/IO53PDB1 IO52NDB1 GCB2/IO52PDB1 VCC GFB2/IO106PDB3 GFC2/IO105PSB3 GEC1/IO100PDB3 VCC IO79RSB2 IO65RSB2 GDB2/IO62RSB2 GDC0/IO58VPB1 VCCIB1 IO54PSB1 VCC GEB1/IO99PDB3 IO106NDB3 VCCIB3 GEC0/IO100NDB3 IO88RSB2 IO81RSB2 VCC TCK GDA2/IO61RSB2 TDO GDA1/IO60UDB1 GDB1/IO59UDB1 v1.0 3-9 Package Pin Assignments 144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P250 Function GEB0/IO99NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 GEA2/IO97RSB2 IO90RSB2 IO84RSB2 GND IO66RSB2 GDC2/IO63RSB2 GND GDA0/IO60VDB1 GDB0/IO59VDB1 GND VMV3 GEB2/IO96RSB2 IO91RSB2 VCCIB2 IO82RSB2 IO80RSB2 IO72RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO95RSB2 IO92RSB2 IO89RSB2 IO87RSB2 IO85RSB2 IO78RSB2 IO76RSB2 TDI VCCIB2 VPUMP GNDQ 3 -1 0 v1.0 Automotive ProASIC3 Packaging 144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P1000 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO10RSB0 GND IO44RSB0 VCC IO69RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GNDQ GAB2/IO224PDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO13RSB0 IO26RSB0 IO35RSB0 IO60RSB0 GBB0/IO74RSB0 GBB1/IO75RSB0 GND VMV1 IO224NDB3 GFA2/IO206PPB3 GAC2/IO223PDB3 VCC IO16RSB0 IO29RSB0 IO32RSB0 IO63RSB0 IO66RSB0 GBA2/IO78PDB1 IO78NDB1 GBC2/IO80PPB1 144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P1000 Function IO213PDB3 IO213NDB3 IO223NDB3 GAA2/IO225PPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO72RSB0 GBC1/IO73RSB0 GBB2/IO79PDB1 IO79NDB1 IO80NPB1 GCB1/IO92PPB1 VCC GFC0/IO209NDB3 GFC1/IO209PDB3 VCCIB3 IO225NPB3 VCCIB0 VCCIB0 GCC1/IO91PDB1 VCCIB1 VCC GCA0/IO93NDB1 IO94NDB1 GFB0/IO208NPB3 VCOMPLF GFB1/IO208PPB3 IO206NPB3 GND GND GND GCC0/IO91NDB1 GCB0/IO92NPB1 GND GCA1/IO93PDB1 GCA2/IO94PDB1 144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P1000 Function GFA1/IO207PPB3 GND VCCPLF GFA0/IO207NPB3 GND GND GND GDC1/IO111PPB1 IO96NDB1 GCC2/IO96PDB1 IO95NDB1 GCB2/IO95PDB1 VCC GFB2/IO205PDB3 GFC2/IO204PSB3 GEC1/IO190PDB3 VCC IO105PDB1 IO105NDB1 GDB2/IO115RSB2 GDC0/IO111NPB1 VCCIB1 IO101PSB1 VCC GEB1/IO189PDB3 IO205NDB3 VCCIB3 GEC0/IO190NDB3 IO160RSB2 IO157RSB2 VCC TCK GDA2/IO114RSB2 TDO GDA1/IO113PDB1 GDB1/IO112PDB1 v1.0 3 - 11 Package Pin Assignments 144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P1000 Function GEB0/IO189NDB3 GEA1/IO188PDB3 GEA0/IO188NDB3 GEA2/IO187RSB2 IO169RSB2 IO152RSB2 GND IO117RSB2 GDC2/IO116RSB2 GND GDA0/IO113NDB1 GDB0/IO112NDB1 GND VMV3 GEB2/IO186RSB2 IO172RSB2 VCCIB2 IO153RSB2 IO144RSB2 IO140RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO185RSB2 IO173RSB2 IO168RSB2 IO161RSB2 IO156RSB2 IO145RSB2 IO141RSB2 TDI VCCIB2 VPUMP GNDQ 3 -1 2 v1.0 Automotive ProASIC3 Packaging 256-Pin FBGA A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 654 321 A B C D E F G H J K L M N P R T Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.0 3 - 13 Package Pin Assignments 256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 A3P250 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO07RSB0 IO10RSB0 IO11RSB0 IO15RSB0 IO20RSB0 IO25RSB0 IO29RSB0 IO33RSB0 GBB1/IO38RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GND GAB2/IO117UDB3 GAA2/IO118UDB3 NC GAB1/IO03RSB0 IO06RSB0 IO09RSB0 IO12RSB0 IO16RSB0 IO21RSB0 IO26RSB0 IO30RSB0 GBC1/IO36RSB0 GBB0/IO37RSB0 NC GBA2/IO41PDB1 IO41NDB1 IO117VDB3 IO118VDB3 NC NC 256-Pin FBGA Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 A3P250 Function GAC0/IO04RSB0 GAC1/IO05RSB0 IO13RSB0 IO17RSB0 IO22RSB0 IO27RSB0 IO31RSB0 GBC0/IO35RSB0 IO34RSB0 NC IO42NPB1 IO44PDB1 IO114VDB3 IO114UDB3 GAC2/IO116UDB3 NC GNDQ IO08RSB0 IO14RSB0 IO18RSB0 IO23RSB0 IO28RSB0 IO32RSB0 GNDQ NC GBB2/IO42PPB1 NC IO44NDB1 IO113PDB3 NC IO116VDB3 IO115UDB3 VMV0 VCCIB0 VCCIB0 IO19RSB0 256-Pin FBGA Pin Number E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P250 Function IO24RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO43PDB1 IO46RSB1 NC IO45PDB1 IO113NDB3 IO112PPB3 NC IO115VDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO43NDB1 NC IO47PPB1 IO45NDB1 IO111NDB3 IO111PDB3 IO112NPB3 GFC1/IO110PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 3 -1 4 v1.0 Automotive ProASIC3 Packaging 256-Pin FBGA Pin Number G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 A3P250 Function GCC1/IO48PPB1 IO47NPB1 IO54PDB1 IO54NDB1 GFB0/IO109NPB3 GFA0/IO108NDB3 GFB1/IO109PPB3 VCOMPLF GFC0/IO110NPB3 VCC GND GND GND GND VCC GCC0/IO48NPB1 GCB1/IO49PPB1 GCA0/IO50NPB1 NC GCB0/IO49NPB1 GFA2/IO107PPB3 GFA1/IO108PDB3 VCCPLF IO106NDB3 GFB2/IO106PDB3 VCC GND GND GND GND VCC GCB2/IO52PPB1 GCA1/IO50PPB1 GCC2/IO53PPB1 NC GCA2/IO51PDB1 256-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 A3P250 Function GFC2/IO105PDB3 IO107NPB3 IO104PPB3 NC VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO52NPB1 IO55RSB1 IO53NPB1 IO51NDB1 IO105NDB3 IO104NPB3 NC IO102RSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO59VPB1 IO57VDB1 IO57UDB1 IO56PDB1 IO103PDB3 NC IO101NPB3 GEC0/IO100NPB3 256-Pin FBGA Pin Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 A3P250 Function VMV3 VCCIB2 VCCIB2 NC IO74RSB2 VCCIB2 VCCIB2 VMV2 NC GDB1/IO59UPB1 GDC1/IO58UDB1 IO56NDB1 IO103NDB3 IO101PPB3 GEC1/IO100PPB3 NC GNDQ GEA2/IO97RSB2 IO86RSB2 IO82RSB2 IO75RSB2 IO69RSB2 IO64RSB2 GNDQ NC VJTAG GDC0/IO58VDB1 GDA1/IO60UDB1 GEB1/IO99PDB3 GEB0/IO99NDB3 NC NC IO92RSB2 IO89RSB2 IO85RSB2 IO81RSB2 v1.0 3 - 15 Package Pin Assignments 256-Pin FBGA Pin Number P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 A3P250 Function IO76RSB2 IO71RSB2 IO66RSB2 NC TCK VPUMP TRST GDA0/IO60VDB1 GEA1/IO98PDB3 GEA0/IO98NDB3 NC GEC2/IO95RSB2 IO91RSB2 IO88RSB2 IO84RSB2 IO80RSB2 IO77RSB2 IO72RSB2 IO68RSB2 IO65RSB2 GDB2/IO62RSB2 TDI NC TDO GND IO94RSB2 GEB2/IO96RSB2 IO93RSB2 IO90RSB2 IO87RSB2 IO83RSB2 IO79RSB2 IO78RSB2 IO73RSB2 IO70RSB2 GDC2/IO63RSB2 256-Pin FBGA Pin Number T13 T14 T15 T16 A3P250 Function IO67RSB2 GDA2/IO61RSB2 TMS GND 3 -1 6 v1.0 Automotive ProASIC3 Packaging 256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 A3P1000 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO22RSB0 IO28RSB0 IO35RSB0 IO45RSB0 IO50RSB0 IO55RSB0 IO61RSB0 GBB1/IO75RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GND GAB2/IO224PDB3 GAA2/IO225PDB3 GNDQ GAB1/IO03RSB0 IO17RSB0 IO21RSB0 IO27RSB0 IO34RSB0 IO44RSB0 IO51RSB0 IO57RSB0 GBC1/IO73RSB0 GBB0/IO74RSB0 IO71RSB0 GBA2/IO78PDB1 IO81PDB1 IO224NDB3 IO225NDB3 VMV3 IO11RSB0 256-Pin FBGA Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 A3P1000 Function GAC0/IO04RSB0 GAC1/IO05RSB0 IO25RSB0 IO36RSB0 IO42RSB0 IO49RSB0 IO56RSB0 GBC0/IO72RSB0 IO62RSB0 VMV0 IO78NDB1 IO81NDB1 IO222NDB3 IO222PDB3 GAC2/IO223PDB3 IO223NDB3 GNDQ IO23RSB0 IO29RSB0 IO33RSB0 IO46RSB0 IO52RSB0 IO60RSB0 GNDQ IO80NDB1 GBB2/IO79PDB1 IO79NDB1 IO82NSB1 IO217PDB3 IO218PDB3 IO221NDB3 IO221PDB3 VMV0 VCCIB0 VCCIB0 IO38RSB0 256-Pin FBGA Pin Number E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P1000 Function IO47RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO80PDB1 IO83PPB1 IO86PPB1 IO87PDB1 IO217NDB3 IO218NDB3 IO216PDB3 IO216NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO83NPB1 IO86NPB1 IO90PPB1 IO87NDB1 IO210PSB3 IO213NDB3 IO213PDB3 GFC1/IO209PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 v1.0 3 - 17 Package Pin Assignments 256-Pin FBGA Pin Number G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 A3P1000 Function GCC1/IO91PPB1 IO90NPB1 IO88PDB1 IO88NDB1 GFB0/IO208NPB3 GFA0/IO207NDB3 GFB1/IO208PPB3 VCOMPLF GFC0/IO209NPB3 VCC GND GND GND GND VCC GCC0/IO91NPB1 GCB1/IO92PPB1 GCA0/IO93NPB1 IO96NPB1 GCB0/IO92NPB1 GFA2/IO206PSB3 GFA1/IO207PDB3 VCCPLF IO205NDB3 GFB2/IO205PDB3 VCC GND GND GND GND VCC GCB2/IO95PPB1 GCA1/IO93PPB1 GCC2/IO96PPB1 IO100PPB1 GCA2/IO94PSB1 256-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 A3P1000 Function GFC2/IO204PDB3 IO204NDB3 IO203NDB3 IO203PDB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO95NPB1 IO100NPB1 IO102NDB1 IO102PDB1 IO202NDB3 IO202PDB3 IO196PPB3 IO193PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO112NPB1 IO106NDB1 IO106PDB1 IO107PDB1 IO197NSB3 IO196NPB3 IO193NPB3 GEC0/IO190NPB3 256-Pin FBGA Pin Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 A3P1000 Function VMV3 VCCIB2 VCCIB2 IO147RSB2 IO136RSB2 VCCIB2 VCCIB2 VMV2 IO110NDB1 GDB1/IO112PPB1 GDC1/IO111PDB1 IO107NDB1 IO194PSB3 IO192PPB3 GEC1/IO190PPB3 IO192NPB3 GNDQ GEA2/IO187RSB2 IO161RSB2 IO155RSB2 IO141RSB2 IO129RSB2 IO124RSB2 GNDQ IO110PDB1 VJTAG GDC0/IO111NDB1 GDA1/IO113PDB1 GEB1/IO189PDB3 GEB0/IO189NDB3 VMV2 IO179RSB2 IO171RSB2 IO165RSB2 IO159RSB2 IO151RSB2 3 -1 8 v1.0 Automotive ProASIC3 Packaging 256-Pin FBGA Pin Number P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 A3P1000 Function IO137RSB2 IO134RSB2 IO128RSB2 VMV1 TCK VPUMP TRST GDA0/IO113NDB1 GEA1/IO188PDB3 GEA0/IO188NDB3 IO184RSB2 GEC2/IO185RSB2 IO168RSB2 IO163RSB2 IO157RSB2 IO149RSB2 IO143RSB2 IO138RSB2 IO131RSB2 IO125RSB2 GDB2/IO115RSB2 TDI GNDQ TDO GND IO183RSB2 GEB2/IO186RSB2 IO172RSB2 IO170RSB2 IO164RSB2 IO158RSB2 IO153RSB2 IO142RSB2 IO135RSB2 IO130RSB2 GDC2/IO116RSB2 256-Pin FBGA Pin Number T13 T14 T15 T16 A3P1000 Function IO120RSB2 GDA2/IO114RSB2 TMS GND v1.0 3 - 19 Package Pin Assignments 484-Pin FBGA A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -2 0 v1.0 Automotive ProASIC3 Packaging 484-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 A3P1000 Function GND GND VCCIB0 IO07RSB0 IO09RSB0 IO13RSB0 IO18RSB0 IO20RSB0 IO26RSB0 IO32RSB0 IO40RSB0 IO41RSB0 IO53RSB0 IO59RSB0 IO64RSB0 IO65RSB0 IO67RSB0 IO69RSB0 NC VCCIB0 GND GND GND VCCIB3 NC IO06RSB0 IO08RSB0 IO12RSB0 IO15RSB0 IO19RSB0 IO24RSB0 IO31RSB0 IO39RSB0 IO48RSB0 IO54RSB0 IO58RSB0 484-Pin FBGA* Pin Number B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 A3P1000 Function IO63RSB0 IO66RSB0 IO68RSB0 IO70RSB0 NC NC VCCIB1 GND VCCIB3 IO220PDB3 NC NC GND IO10RSB0 IO14RSB0 VCC VCC IO30RSB0 IO37RSB0 IO43RSB0 NC VCC VCC NC NC GND NC NC NC VCCIB1 IO219PDB3 IO220NDB3 NC GND GAA0/IO00RSB0 GAA1/IO01RSB0 484-Pin FBGA* Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 A3P1000 Function GAB0/IO02RSB0 IO16RSB0 IO22RSB0 IO28RSB0 IO35RSB0 IO45RSB0 IO50RSB0 IO55RSB0 IO61RSB0 GBB1/IO75RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GND NC NC NC IO219NDB3 NC GND GAB2/IO224PDB3 GAA2/IO225PDB3 GNDQ GAB1/IO03RSB0 IO17RSB0 IO21RSB0 IO27RSB0 IO34RSB0 IO44RSB0 IO51RSB0 IO57RSB0 GBC1/IO73RSB0 GBB0/IO74RSB0 IO71RSB0 GBA2/IO78PDB1 IO81PDB1 GND v1.0 3 - 21 Package Pin Assignments 484-Pin FBGA* Pin Number E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P1000 Function NC IO84PDB1 NC IO215PDB3 IO215NDB3 IO224NDB3 IO225NDB3 VMV3 IO11RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO25RSB0 IO36RSB0 IO42RSB0 IO49RSB0 IO56RSB0 GBC0/IO72RSB0 IO62RSB0 VMV0 IO78NDB1 IO81NDB1 IO82PPB1 NC IO84NDB1 IO214NDB3 IO214PDB3 NC IO222NDB3 IO222PDB3 GAC2/IO223PDB3 IO223NDB3 GNDQ IO23RSB0 IO29RSB0 IO33RSB0 IO46RSB0 484-Pin FBGA* Pin Number G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 A3P1000 Function IO52RSB0 IO60RSB0 GNDQ IO80NDB1 GBB2/IO79PDB1 IO79NDB1 IO82NPB1 IO85PDB1 IO85NDB1 NC NC NC VCC IO217PDB3 IO218PDB3 IO221NDB3 IO221PDB3 VMV0 VCCIB0 VCCIB0 IO38RSB0 IO47RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO80PDB1 IO83PPB1 IO86PPB1 IO87PDB1 VCC NC NC IO212NDB3 IO212PDB3 NC IO217NDB3 484-Pin FBGA* Pin Number J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 A3P1000 Function IO218NDB3 IO216PDB3 IO216NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO83NPB1 IO86NPB1 IO90PPB1 IO87NDB1 NC IO89PDB1 IO89NDB1 IO211PDB3 IO211NDB3 NC IO210PPB3 IO213NDB3 IO213PDB3 GFC1/IO209PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO91PPB1 IO90NPB1 IO88PDB1 3 -2 2 v1.0 Automotive ProASIC3 Packaging 484-Pin FBGA* Pin Number K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 A3P1000 Function IO88NDB1 IO94NPB1 IO98NDB1 IO98PDB1 NC IO200PDB3 IO210NPB3 GFB0/IO208NPB3 GFA0/IO207NDB3 GFB1/IO208PPB3 VCOMPLF GFC0/IO209NPB3 VCC GND GND GND GND VCC GCC0/IO91NPB1 GCB1/IO92PPB1 GCA0/IO93NPB1 IO96NPB1 GCB0/IO92NPB1 IO97PDB1 IO97NDB1 IO99NPB1 NC IO200NDB3 IO206NDB3 GFA2/IO206PDB3 GFA1/IO207PDB3 VCCPLF IO205NDB3 GFB2/IO205PDB3 VCC GND 484-Pin FBGA* Pin Number M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 A3P1000 Function GND GND GND VCC GCB2/IO95PPB1 GCA1/IO93PPB1 GCC2/IO96PPB1 IO100PPB1 GCA2/IO94PPB1 IO101PPB1 IO99PPB1 NC IO201NDB3 IO201PDB3 NC GFC2/IO204PDB3 IO204NDB3 IO203NDB3 IO203PDB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO95NPB1 IO100NPB1 IO102NDB1 IO102PDB1 NC IO101NPB1 IO103PDB1 NC IO199PDB3 484-Pin FBGA* Pin Number P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 A3P1000 Function IO199NDB3 IO202NDB3 IO202PDB3 IO196PPB3 IO193PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO112NPB1 IO106NDB1 IO106PDB1 IO107PDB1 NC IO104PDB1 IO103NDB1 NC IO197PPB3 VCC IO197NPB3 IO196NPB3 IO193NPB3 GEC0/IO190NPB3 VMV3 VCCIB2 VCCIB2 IO147RSB2 IO136RSB2 VCCIB2 VCCIB2 VMV2 IO110NDB1 v1.0 3 - 23 Package Pin Assignments 484-Pin FBGA* Pin Number R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 A3P1000 Function GDB1/IO112PPB1 GDC1/IO111PDB1 IO107NDB1 VCC IO104NDB1 IO105PDB1 IO198PDB3 IO198NDB3 NC IO194PPB3 IO192PPB3 GEC1/IO190PPB3 IO192NPB3 GNDQ GEA2/IO187RSB2 IO161RSB2 IO155RSB2 IO141RSB2 IO129RSB2 IO124RSB2 GNDQ IO110PDB1 VJTAG GDC0/IO111NDB1 GDA1/IO113PDB1 NC IO108PDB1 IO105NDB1 IO195PDB3 IO195NDB3 IO194NPB3 GEB1/IO189PDB3 GEB0/IO189NDB3 VMV2 IO179RSB2 IO171RSB2 484-Pin FBGA* Pin Number U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 A3P1000 Function IO165RSB2 IO159RSB2 IO151RSB2 IO137RSB2 IO134RSB2 IO128RSB2 VMV1 TCK VPUMP TRST GDA0/IO113NDB1 NC IO108NDB1 IO109PDB1 NC NC GND GEA1/IO188PDB3 GEA0/IO188NDB3 IO184RSB2 GEC2/IO185RSB2 IO168RSB2 IO163RSB2 IO157RSB2 IO149RSB2 IO143RSB2 IO138RSB2 IO131RSB2 IO125RSB2 GDB2/IO115RSB2 TDI GNDQ TDO GND NC IO109NDB1 484-Pin FBGA* Pin Number W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 A3P1000 Function NC IO191PDB3 NC GND IO183RSB2 GEB2/IO186RSB2 IO172RSB2 IO170RSB2 IO164RSB2 IO158RSB2 IO153RSB2 IO142RSB2 IO135RSB2 IO130RSB2 GDC2/IO116RSB2 IO120RSB2 GDA2/IO114RSB2 TMS GND NC NC NC VCCIB3 IO191NDB3 NC IO182RSB2 GND IO177RSB2 IO174RSB2 VCC VCC IO154RSB2 IO148RSB2 IO140RSB2 NC VCC 3 -2 4 v1.0 Automotive ProASIC3 Packaging 484-Pin FBGA* Pin Number Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 A3P1000 Function VCC NC NC GND NC NC NC VCCIB1 GND VCCIB3 NC IO181RSB2 IO178RSB2 IO175RSB2 IO169RSB2 IO166RSB2 IO160RSB2 IO152RSB2 IO146RSB2 IO139RSB2 IO133RSB2 NC NC IO122RSB2 IO119RSB2 IO117RSB2 NC NC VCCIB1 GND GND GND VCCIB2 IO180RSB2 IO176RSB2 IO173RSB2 484-Pin FBGA* Pin Number AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 A3P1000 Function IO167RSB2 IO162RSB2 IO156RSB2 IO150RSB2 IO145RSB2 IO144RSB2 IO132RSB2 IO127RSB2 IO126RSB2 IO123RSB2 IO121RSB2 IO118RSB2 NC VCCIB2 GND GND v1.0 3 - 25 Package Pin Assignments Part Number and Revision Date Part Number 51700099-003-0 Revised January 2008 Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 3 -2 6 v1.0 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. w w w. a c t e l . c o m Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 Actel Japan EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn 51700099-005-0/1.08 |
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